Comparator Circuit (2-bit, 4-bit, 8-bit) VHDL code (A comparator compares two n-bit inputs and generates three status signals)

Project specification:
A comparator compares two n-bit inputs and generates three status signals. The input and
output signals are
   input:

a: n-bit input operand
b: n-bit input operand
  output:

lt: 1-bit output. It is asserted when a is larger than b.
st: 1-bit output. It is asserted when a is smaller than b.
eq: 1-bit output. It is asserted when a is equal to than b.


Design Procedures:

   1. 2-bit comparator
In a 2-bit comparator, the input size of an operand (i.e., n) is 2. The circuit should have four inputs and three outputs.

   2.4-bit comparator

In a 4-bit comparator, the input size of an operand (i.e., n) is 4. The circuit should have eight inputs and three outputs. The circuit can be constructed from two 2-bit comparators of theprevious section.

   3. 4-bit comparator with 7-segment display
An additional seven-segment LED display can be used to show the output status. The display will show “L”, “E” or “S” pattern for the larger-than, equal-to, or smaller-than condition. Conditional signal assignment or selected signal assignment statements can be used for the 7- sgement LED circuit.

   4. 8-bit comparator
In an 8-bit comparator, the input size of an operand (i.e., n) is 8. The circuit should have 16 inputs and three outputs. The circuit can be constructed from the previously designed comparators.

2-bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp2 is
port(
a,b: in std_logic_vector(1 downto 0);
lt, st, eq: out std_logic
);
end comp2;
architecture bit2_Comparator of comp2 is
signal p0,p1,p2,p3,p4,p5,p6,p7,p8,p9: std_logic;
begin
eq <= p0 or p1 or p2 or p3;
p0 <= ( (not a(1)) and (not a(0)) and (not b(1)) and (not b(0)) );
p1 <= ( (not a(1)) and a(0) and (not b(1)) and b(0) );
p2 <= ( a(1) and (not a(0)) and b(1) and (not b(0)) );
p3 <= ( a(1) and a(0) and b(1) and b(0) );
st <= p4 or p5 or p6;
p4 <= ( (not a(0)) and b(1) and b(0) );
p5 <= ( (not a(1)) and (not a(0)) and b(0) );
p6 <= ( (not a(1)) and b(1) );
lt <= p7 or p8 or p9;
p7 <= ( a(1) and a(0) and (not b(0)) );
p8 <= ( a(1) and (not b(1)) );
p9 <= ( a(0) and (not b(1)) and (not b(0)) );
end bit2_Comparator;

4-Bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(
a,b: in std_logic_vector(3 downto 0);
lt, st, eq: out std_logic;
LED: out std_logic_vector(6 downto 0)
);
end comp4;
architecture bit4_Comparator of comp4 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(3), a(0)=>a(2), b(1)=>b(3), b(0)=>b(2), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(1), a(0)=>a(0), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
end bit4_Comparator;

4-bit comparator with 7-segment display:

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(
a,b: in std_logic_vector(3 downto 0);
lt, st, eq: out std_logic;
LED: out std_logic_vector(6 downto 0)
);
end comp4;
architecture bit4_Comparator of comp4 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(3), a(0)=>a(2), b(1)=>b(3), b(0)=>b(2), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(1), a(0)=>a(0), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
LED(6) <= l1 or (e1 and l0);
LED(4) <= s1 or (e1 and s0);
LED(2) <= l1 or (e1 and l0) or (e1 and e0);
LED(1) <= e1 or l1 or s1;
LED(0) <= l1 or (e1 and l0);

   sseg_unit: entity work.hex_toshow_LES(arch)
port map(s=>st, l=>lt, sseg=>LED);
"0001000" when (l='1') else  --larger
"0010010" when (s='1') else --smaller
"0000110";
end bit4_Comparator;

8-bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp8 is
port(
a,b: in std_logic_vector(7 downto 0);
lt, st, eq: out std_logic
);
end comp8;
architecture bit8_Comparator of comp8 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(7), a(2)=>a(6), a(1)=>a(5), a(0)=>a(4), b(3)=>b(7), b(2)=>b(6), b(1)=>b(5), b(0)=>b(4), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(3), a(2)=>a(2), a(1)=>a(1), a(0)=>a(0), b(3)=>b(3), b(2)=>b(2), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
end bit8_Comparator;