Programming Pointers Definition C/C++ (Learn what are pointers? How defined and used using sample example pointer code in C++)

Pointers Definition: A pointer is a data type recognized by C++ and C, but not by Java. A variable of data type pointer contains an address of some other data element stored in data memory (RAM), e.g., the address of the value stored in some other variable. The pointer variable itself is also stored at some address in data memory.


Diagram to learn programming pointers: 

Pointers in different computer programming languages: 


Pointers in C++/C: A pointer variable contains the address of other data elements. The values stored at the address can be changed, copied, etc., using only the address. Advantage of pointers in C/C++ is that programmers can directly access memory locations of the variables assigned while programming application programs either for embedded systems or operating system programs. Pointers should be used very carefully while programming your application in C/C++ since mirror error in pointer can terminate your whole application.

Pointers in Java: Java programmer does not have access to pointers. Pointers are used implicitly by the Java compiler/interpreter. Actually used more frequently by the Java compiler/interpreter than by the either the C++ or C compiler. Explicit manipulation of addresses/pointers by the Java programmer is forbidden. 

Now lets simply understand how pointers are defined and used in C++ using simple example for better understanding pointers for practical purposes:
STEP 1: float A;
1. First of all, the data type of variable A is float.
2. The variable name A is for human/programmer use only. The compiler converts the variable name into an address/pointer that is used by the compiled code to access the value stored at that address.
3. The variable name is converted by the compiler into an address in data memory.
4. The address that is synonymous with to the variable name A contains the value that has been assigned to that variable.
5. Normally the code that manipulates the address that corresponds to the variable A is hidden from the programmer. 6. If desired by the programmer that address can be accessed, again it is only possible in C and C++ but not in JAVA. Variable address can be accessed using:
a. A reference to the variable A, as in &A.
b. A pointer to A (explained below).

STEP 2: float* PtrToA;
1. The notation float* defines the data type of pointer-to-float.
2. The variable name which follows is, then, the name of a variable which holds a value which is the address of some floating point value.
3. Alternate notation: float *PtrToA;

STEP 3: A = 3.1415;
1. Standard assignment statement.
2. The constant value 3.1415 is stored at the address in RAM that corresponds to the variable A.


STEP 4: PtrToA = &A;
1. A slightly different assignment statement.
2. The notation &A designates the address of the variable A.
3. Therefore: PtrToA = &A; causes the address of the variable A to be loaded into the address in RAM that corresponds to the pointer variable PtrToA.

In the end, lets program in C++ what we have explained above about pointers usage to see the actual results in programming how pointers are defined inside computer memory and how pointers are used inside the computer programming.

Samle example Code:

#include <iostream>
using namespace std; 

void main() 

{

float A; // declaration of a floating point variable 

// allocates four bytes of RAM and attaches // the memory to the program. 

          float* PtrToA; // declaration of a variable that will hold the

// address of a floating point number. 

          A = 3.1415; // Assign a value to the floating point variable, i.e., store a value at the address

// in RAM that is synonymous with the  variable name. 

          PtrToA = &A; // The value assigned to the pointer variable is the address of the floating point variable

          cout << endl << "The value of A is " << A << " while the address of A is " << PtrToA << endl << "                and the value stored at the address " << PtrToA << " is " << *PtrToA << endl;

         *PtrToA = 89.526;

          cout << endl << "The value of A is " << A << " while the address of A is " << PtrToA << endl << " and the value stored at the address " << PtrToA << " is " << *PtrToA << endl;

} 

The output of the above sample code to understand pointers would be:


The value of A is 3.1415 while the address of A is 0012FF7C and the value stored at the address 0012FF7C is 3.1415 
The value of A is 89.526 while the address of A is 0012FF7C and the value stored at the address 0012FF7C is 89.526

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FSM VHDL Lab Code for Thunderbird Turn Signal circuit design (FPGA Digital Systems Project Explanation)

Using Thunderbird Turn Signal digital circuit lab, you can learn how the logic of finite state machine is implemented in real life embedded world for example in this case, 1965 Ford Thunderbird. FSM's contributes a lot more functionality to the world of Digital Systems. 

SO What is FSM (finite-state machine): A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible transition states from each current state, and the triggering condition for each transition.

Now after getting familiar with FSM, lets practice programming it in VHDL language using Thunderbird Turn Signal fsm design circuit lab.

Project specification: The tail lights of a 1965 Ford Thunderbird is shown below. There are three lights on each side that operate in sequence to indicate the direction of a turn. There are three flashing sequence: left turn, right turn, and hazard.

The left-turn sequence is:

The right-turn sequence is similar and represents a “mirror” sequence of the left-turn pattern. In the hazard sequence, the six lights flash on and off alternatively. In all sequences, we assume that each pattern stays for 300 ms.

A simple FSM can be constructed to control the tail light operation. The input and output of the thunderbird turn signal lab are as follows:

Input:

 clk: 50 MHz clock signal from the DE1 board.

 reset

 tick: 1-bit 300ms “tick” signal. It is asserted for one clock cycle every 300 ms.

 left: 1-bit left-turn signal.

 right: 1-bit right-turn signal.

 haz: 1-bit hazard signal.

Output:

 light: 6-bit light signal.

The Thunderbird Turn Signal digital design circuit lab system operates as follows:

11.> Anytime haz is asserted, the FSM enters the hazard sequence immediately. If the FSM currently in the middle of a left- or right-turn, sequence, the sequence will be aborted.

22.> When haz is not asserted and left is asserted and, the FSM goes through the complete left-turn sequence. This means that the lights should go through a complete left-turn sequence even if left is de asserted sometime in the middle of the sequence or if right is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

33.> When haz is not asserted and right is asserted and, the FSM goes through the complete right-turn sequence. This means that the lights should go through a complete right-turn sequence even if right is de-asserted sometime in the middle of the sequence or if left is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

44.> We assume that left and right will never be asserted simultaneously.

Design Procedures: We can divide this circuit into two segments: 

Counter: generate a one-clock pulse (tick) every 300 ms. 

=>> I have explained how to achieve counter functionality in previous post(you can find them there: digital systems labs). 

FSM: 

=>> Convert the state diagram to an ASM chart following the notations used in the text. Once done with state diagrams, design the FSM as an independent VHDL module.  The entity declaration of this design is    

entity tbird_fsm is

   port(

   clk, reset: std_logic;

   tick, left, right, haz: std_logic;

   light: out std_logic_vector(5 downto 0);

    );

  END tbird_fsm;

After that we will also need to derive the architecture body which will be added below in whole program code. 

Thunderbird lab VHDL code for implementing tail light FSM digital systems circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lights is
   port(
      clk, reset: in std_logic;
      l, r, h: in std_logic;
      light: out std_logic_vector(5 downto 0)
   );
end lights;
architecture arch of lights is
   constant DVSR: integer:=5000000;
   signal ms_reg, ms_next: unsigned(22 downto 0);
 
   type eg_state_type is (s0, sh1, sh2, sl1, sl2, sl3, sr1, sr2, sr3);
   signal state_reg, state_next: eg_state_type;
begin
  process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
-- d0_reg <= d0_next;
      end if;
   end process;
ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
 -- state register
   process(reset,clk,ms_reg,state_reg)
   begin
      if (reset='1') then
         state_reg <= s0;
      elsif (clk='1' and clk'event) then
if (ms_reg=DVSR) then
state_reg <= state_next;
      end if;
end if;
   end process;
   -- next-state logic
   process(state_reg, l, r, h, clk)
   begin
--if tick='1' then
      case state_reg is
        when s0=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sh1=>
state_next <= sh2;
when sh2=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sl1=>
if (h='1') then state_next <= sh1;
else state_next <= sl2;
end if;
when sl2=>
if (h='1') then state_next <= sh1;
else state_next <= sl3;
end if;
when sl3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sr1=>
if (h='1') then state_next <= sh1;
else state_next <= sr2;
end if;
when sr2=>
if (h='1') then state_next <= sh1;
else state_next <= sr3;
end if;
when sr3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
      end case;
--end if;
end process;
   -- Moore output logic
   process(state_reg)
   begin
      case state_reg is
         when s0 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sh1 =>
-- if tick='1' then
            light <= "111111";
-- end if;
         when sh2 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sl1 =>
-- if tick='1' then
            light <= "001000";
-- end if;
         when sl2 =>
-- if tick='1' then
            light <= "011000";
-- end if; when sl3 =>
-- if tick='1' then
            light <= "111000";
-- end if;
         when sr1 =>
-- if tick='1' then
            light <= "000100";
-- end if; when sr2 =>
-- if tick='1' then
            light <= "000110";
-- end if;
when sr3 =>
-- if tick='1' then
            light <= "000111";
-- end if;
      end case;
   end process;
end arch;

   

Then obviously compile the design and perform simulation to verify its operation. I used EP2C20F484C8 Cyclone ii FPGA Starter board for implementation of Thunderbird Turn Signal FSM digital circuit design.

Implementation and testing:

You will use the 50MHz oscillator for clock and 4 switches for the reset signal and three control signals. You could use any FPGA board but I have compiled and tested the code on Altera provided FPGA board. I have posted below the pin assignments I used for my EP2C20F484C8 Cyclone ii FPGA Starter board:

From	To	Assignment Name	Value	Enabled
	reset	Location	PIN_L22	Yes
	h	Location	PIN_L21	Yes
	r	Location	PIN_M22	Yes
	l	Location	PIN_V12	Yes
	clk	Location	PIN_L1	Yes
	light[0]	Location	PIN_R20	Yes
	light[1]	Location	PIN_R19	Yes
	light[2]	Location	PIN_U19	Yes
	light[3]	Location	PIN_Y19	Yes
	light[4]	Location	PIN_T18	Yes
	light[5]	Location	PIN_V19	Yes

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Rotating LED VHDL Lab Code With Intermediate-Sized Sequential Circuit Project Design and Procedures

Rotating LED is an intermediate-sized sequential circuit. Rotating LED lab will utilize seven-segment LED and clock functionality. VHDL language is used to implement this rotating LED logic on Altera DE1 FPGA device using  Altera Quartus design suite.

Project specification: In a seven-segment LED display, a square pattern can be created by enabling the a, b, f, and g segments or the c, d, e, and g segments. We want to design a circuit that circulates the square patterns in the four-digit seven-segment LED display. The circulating pattern could either be clockwise or counter-clockwise depending on the user input. The clockwise circulating pattern is shown above, just to give you an idea how we want to implement our rotating LED circuit logic. The control signals of the circuit can specify the rotation speed, the direction of rotation (i.e., clockwise or counterclockwise), and pause the operation. The rotating LED circuit design must be synchronous. We will use 4 switches for the control signals and 50MHz oscillator for clock from DE1 Altera FPGA board. The input and output signals for rotating LED logic circuit will be as follows:

Inputs:
• clk: 50 MHz clock signal from the DE1 board.
• pa: 1-bit enable signal. The circulation pauses when it is 1.
• cw: 1-bit direction signal. The pattern circulates clockwise when it is 1 and counter
clockwise when it is 0.
• sp: 2-bit speed control:
• 00: each pattern stays 20 ms
• 01: each pattern stays 40 ms
• 10: each pattern stays 80 ms
• 11: each pattern stays 160 ms

Output:
• Four seven-segment LED displays.

Design Procedures: We can divide rotating LED circuit into four segments and finally we can add up a wrapping VHDL code to instantiate all the modules. Lets first go through each module required to do the rotating LED circuit lab with the VHDL code provided:

Counter 1: generate a one-clock pulse (tick1) every 10 ms.


VHDL module Code to generate one clock pulse every 10 ms:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_1 is
   port(
      clk: in std_logic;
      tick1: out std_logic
   );
end counter_1;
architecture arch of counter_1 is
   constant DVSR: integer:=500000;
   signal ms_reg, ms_next: unsigned(18 downto 0);
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01(10ms) sec tick generator: mod-500000
   ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
   tick1 <= '1' when ms_reg=DVSR else '0';
end arch;   

Counter 2: utilizes tick1 pulse and generates a one-clock pulse (tick2) every 20 ms, 40 ms, 80 ms or 160 ms based on the sp input signal.

VHDL module Code to control the speed of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_2 is
   port(
      clk: in std_logic;
tick1: in std_logic;
sp: in std_logic_vector(1 downto 0);
      tick2: out std_logic
   );
end counter_2;
architecture arch of counter_2 is
   signal d1_reg, d0_reg: unsigned(3 downto 0);
   signal d1_next, d0_next: unsigned(3 downto 0);
   signal d1_en, d0_en: std_logic;
   signal d0_tick, tick_20ms, tick_40ms, tick_80ms, tick_160ms: std_logic;
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         d1_reg <= d1_next;
         d0_reg <= d0_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01 sec counter
   d0_en <= '1' when tick1='1' else '0';
   d0_next <=
      "0000" when (d0_en='1' and d0_reg=15) else
      d0_reg + 1 when d0_en='1' else
      d0_reg;
    tick_20ms <= '1' when d0_reg=2 else '0';
tick_40ms <= '1' when d0_reg=4 else '0';
tick_80ms <= '1' when d0_reg=8 else '0';
d0_tick <= '1' when d0_reg=9 else '0';
   -- .1 sec counter
   d1_en <= '1' when tick1='1' and d0_tick='1' else '0';
   d1_next <=
      "0000" when (d1_en='1' and d1_reg=9) else
      d1_reg + 1 when d1_en='1' else
      d1_reg;
   tick_160ms <= '1' when (d1_reg=1 and d0_reg=6) else '0';
   -- output logic
with sp select
      tick2 <=   tick_20ms when "00",
                 tick_40ms when "01",
                 tick_80ms when "10",
                 tick_160ms when others;
end arch;

Counter 3: mod-8 counter that utilizes tick2 pulse and can pause, count up and count down.

VHDL module Code for mod 8 counter to control the direction of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_3 is
   generic(
      N: integer := 3;     -- number of bits
      M: integer := 8      -- mod-M
  );
   port(
      clk: in std_logic;
      tick2, cw, pa: in std_logic;
      q: out std_logic_vector(N-1 downto 0)
   );
end counter_3;
architecture arch of counter_3 is
   signal r_regf, r_reg1, r_reg2: unsigned(N-1 downto 0);
   signal r_nextf, r_next1, r_next2: unsigned(N-1 downto 0);
begin
   -- register
   process(clk,pa)
   begin
      if (clk'event and clk='1' and tick2='1' and pa='0') then
         r_regf <= r_nextf;
         r_reg1 <= r_next1;
         r_reg2 <= r_next2;
end if;
   end process;
   -- next-state logic
r_next1 <= (others=>'0') when r_reg1=(M-1) else
             r_reg1 + 1;
r_next2 <= (others=>'1') when r_reg2=(0) else
             r_reg2 - 1;
r_nextf <= r_next1 when(cw='1') else
 r_next2;
-- output logic
   q <= std_logic_vector(r_regf);
end arch;

Decoding Circuit: A decoding circuit that generates the desired LED patterns.

VHDL module code for decoding rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
entity decoder_rotatingLED is
port
(
input: in std_logic_vector(2 downto 0);
en: out std_logic_vector(27 downto 0)
);
end decoder_rotatingLED;
architecture arch of decoder_rotatingLED is
begin
process(input)
begin
case input  is
            when "000" =>   en <= "0011100111111111111111111111";
            when "001" =>   en <= "1111111001110011111111111111";
            when "010" =>   en <= "1111111111111100111001111111";
            when "011" =>   en <= "1111111111111111111110011100";
            when "100" =>   en <= "1111111111111111111110100011";
            when "101" =>   en <= "1111111111111101000111111111";
            when "110" =>   en <= "1111111010001111111111111111";
            when "111" =>   en <= "0100011111111111111111111111";
end case;
end process;
end arch;

Final Wrapping up circuit for rotating LED circuit which will instantiate all the modules defined above(counter1, counter2, counter3, decoding circuit). In Altera Quartus design suite, this final rotatingLED VHDL module will be set as top level entity declaration before compiling.

VHDL module Code for rotatingLED is:

library ieee;
use ieee.std_logic_1164.all;
entity rotatingLED is
port
(
final_clk: in std_logic;
final_pa, final_cw: in std_logic;
final_sp: in std_logic_vector(1 downto 0);
hex3, hex2, hex1, hex0: out std_logic_vector(6 downto 0)
);
end rotatingLED;
architecture arch of rotatingLED is
signal temp0, temp1: std_logic;
signal temp2: std_logic_vector(2 downto 0);
signal cycle: std_logic_vector(27 downto 0);
begin
c1_unit: entity work.counter_1(arch)
port map(clk=>final_clk, tick1=>temp0);
c2_unit: entity work.counter_2(arch)
port map(clk=>final_clk, tick1=>temp0, sp=>final_sp, tick2=>temp1);
c3_unit: entity work.counter_3(arch)
port map(clk=>final_clk, tick2=>temp1, pa=>final_pa, cw=>final_cw, q=>temp2);
decoder_rotatingLED_unit: entity work.decoder_rotatingLED(arch)
port map(input=>temp2, en=>cycle);
hex3 <= cycle(27 downto 21);
hex2 <= cycle(20 downto 14);
hex1 <= cycle(13 downto 7);
hex0 <= cycle(6 downto 0);
end arch;

We will also do the pin assignment for this rotating LED circuit lab as follows:

From	To	Assignment Name	Value	Enabled
	final_pa	Location	PIN_L22	Yes
	final_cw	Location	PIN_L21	Yes
	final_sp[0]	Location	PIN_M22	Yes
	final_sp[1]	Location	PIN_V12	Yes
	final_clk	Location	PIN_L1	Yes
	hex0[0]	Location	PIN_J2	Yes
	hex0[1]	Location	PIN_J1	Yes
	hex0[2]	Location	PIN_H2	Yes
	hex0[3]	Location	PIN_H1	Yes
	hex0[4]	Location	PIN_F2	Yes
	hex0[5]	Location	PIN_F1	Yes
	hex0[6]	Location	PIN_E2	Yes
	hex1[0]	Location	PIN_E1	Yes
	hex1[1]	Location	PIN_H6	Yes
	hex1[2]	Location	PIN_H5	Yes
	hex1[3]	Location	PIN_H4	Yes
	hex1[4]	Location	PIN_G3	Yes
	hex1[5]	Location	PIN_D2	Yes
	hex1[6]	Location	PIN_D1	Yes
	hex2[0]	Location	PIN_G5	Yes
	hex2[1]	Location	PIN_G6	Yes
	hex2[2]	Location	PIN_C2	Yes
	hex2[3]	Location	PIN_C1	Yes
	hex2[4]	Location	PIN_E3	Yes
	hex2[5]	Location	PIN_E4	Yes
	hex2[6]	Location	PIN_D3	Yes
	hex3[0]	Location	PIN_F4	Yes
	hex3[1]	Location	PIN_D5	Yes
	hex3[2]	Location	PIN_D6	Yes
	hex3[3]	Location	PIN_J4	Yes
	hex3[4]	Location	PIN_L8	Yes
	hex3[5]	Location	PIN_F3	Yes
	hex3[6]	Location	PIN_D4	Yes

Please leave your feedback to improve the quality of the code on this site. Check out our selection VHDL related posts and lab codes.

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LINUX/UNIX C Shell Alias Command Syntax Example Code

LINUX/UNIX Aliases:
The C shell allows you to create and customize your own commands by using the built-in command alias. Commonly used for a long strings that are frequently used. Alias allows you to have a small more familiar command or name to execute a long string. An alias will last for the life of the shell session.
Regularly used aliases can be set from the shell's configuration file (~/.cshrc or the systemwide /etc/csh.cshrc for csh, or ~/.bashrc or the systemwide /etc/bashrc or /etc/bash.bashrc for bash) so that they will be available upon the start of the corresponding shell session. The alias commands may either be written in the config file directly or sourced from a separate file, typically named .alias (or .alias-bash, .alias-csh, etc., if multiple shells may be used).

Syntax and description of the alias shell command:

Shell Command: alias [word [string] ]

alias supports a simple form of command-line customization. If you alias word to be equal to string and then later enter a command beginning with word, the first occurrence of word is replaced by string and then the command is reprocessed.
If you don't supply word or string, a list of all the current shell aliases is displayed. If you only supply word, then the string currently associated with the alias word is displayed. If you supply word and string, the shell adds the specified alias to its collection of aliases. If an alias already exists for word, it is replaced.
If the replacement string begins with word, it is not reprocessed for aliases to prevent infinite loops. If the replacement string contains word elsewhere, an error message is displayed when the alias is executed.

To give you some exposure of how alias command works on running linux system, below is an example of alias in action:

$ alias dir 'ls -aF' ...register an alias.
$ dir ...same as typing "ls -aF".
./ main2.c p.reverse.c reverse.h
../ main2.o palindrome.c reverse.old
$ dir *.c ...same as typing "ls -aF *.c".
main2.c p.reverse.c palindrome.c
$ alias dir ...look at the value associated with "dir".
ls -aF
$ _

In the following example, I aliased a word in terms of itself:

% alias ls 'ls -aF' ...define "ls" in terms of itself.
% ls *.c ...same as typing "ls -aF *.c".
main2.c p.reverse.c palindrome.c
% alias dir 'ls' ...define "dir" in terms of "ls".
% dir ...same as typing "ls -aF".
./ main2.c p.reverse.c reverse.h
../ main2.o palindrome.c reverse.old
% alias who 'date; who' ...infinite loop problem.
% who
Alias loop.
% alias who 'date; /usr/bin/who' ...full path avoids error
% who ...works fine now.
Fri May 13 23:33:37 CST 2005
smith ttyp0 Feb 13 23:30 (xyplex2)
% _

Removing an Alias:
To remove an alias, use the built-in command unalias.

Syntax and description of the unalias shell command:
Shell Command: unalias pattern unalias removes all of the aliases that match pattern. If pattern is *, then all aliases are removed.

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