Tuesday, June 26, 2012

Barrel Shifter VHDL Code with diagram to learn

Barrel Shifter: Rotates 8-bit input by a specific amount.
Problem with large input (e.g., 32 bits)
– Large multiplexing structure
– Lengthy code
– Better alternative

Barrel Shifter VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
   port(
      a: in std_logic_vector(7 downto 0);
      amt: in std_logic_vector(2 downto 0);
      y: out std_logic_vector(7 downto 0)
   );
end barrel_shifter ;
architecture sel_arch of barrel_shifter is
begin
   with amt select
      y<= a                             when "000",
          a(0) & a(7 downto 1)          when "001",
          a(1 downto 0) & a(7 downto 2) when "010",
          a(2 downto 0) & a(7 downto 3) when "011",
          a(3 downto 0) & a(7 downto 4) when "100",
          a(4 downto 0) & a(7 downto 5) when "101",
          a(5 downto 0) & a(7 downto 6) when "110",
          a(6 downto 0) & a(7) when others; -- 111
end sel_arch;

Friday, May 25, 2012

What is an Operating System? (Extended Machine and Resource Manager)

WHAT IS AN OPERATING SYSTEM?
I think its hard to pin down what an operating system is other than saying it is the software that runs in kernel mode and even that is not always true. Basically operating systems perform two unrelated functions: providing application programmers a clean abstract set of resources instead of the messy hardware ones and managing these hardware resources.

Therefore, OPERATING SYSTEM = EXTENDED MACHINE + RESOURCE MANAGER

Depending on who is doing the talking, you might hear mostly about one function or the other.

But here we will now look at both.

First case: Extended Machine
The architecture (instruction set, memory organization, I/O, and bus structure) of most computers at the machine language level is primitive and awkward to program, especially for input/output. To make this point more concrete, consider how floppy disk I/O is done using the NEC PD765 compatible controller chips used on most Intel-based personal computers. We use the floppy disk as an example, because, although it is obsolete, it is much simpler than a modem hard disk.

[ The PD765 has 16 commands, each specified by loading between 1 and 9 bytes into a device register. These commands are for reading and writing data, moving the disk arm, and formatting tracks, as well as initializing, sensing, resetting, and recalibrating the controller and the drives. The most basic commands are read and write, each of which requires 13 parameters, packed into 9 bytes. These parameters specify such items as the address of the disk block to be read, the number of sectors per track, the recording mode used on the physical medium, the intersector gap spacing, and what to do with a deleted-data-address-mark. When the operation is completed, the controller chip returns 23 status and error fields packed into 7 bytes. As if this were not enough, the floppy disk programmer must also be constantly aware of whether the motor is on or off. If the motor is off, it must be turned on (with a long startup delay) before data can be read or written. The motor cannot be left on too long, however, or the floppy disk will wear out.]
If you do not understand this mumbo jumbo, do not worry; that is precisely the point-it is rather esoteric. The programmer is thus forced to deal with the trade-off between long startup delays versus wearing out floppy disks (and losing the data on them). Without going into the real details, it should be clear that the average programmer probably does not want to get too intimately involved with the programming of floppy disks (or hard disks, which are worse). Instead, what the programmer wants is a simple, high-level abstraction to deal with.
In the case of disks, a typical abstraction would be that the disk contains a collection of named files. Each file can be opened for reading or writing, then read or written, and finally closed. Details such as whether or not recording should use modified frequency modulation and what the current state of the motor is should not appear in the abstraction presented to the application programmer.

Abstraction is the key to managing complexity. Good abstractions turn a nearly impossible task into two manageable ones. The first one of these is defining and implementing the abstractions. The second one is using these abstractions to solve the problem at hand.
One abstraction that almost every computer user understands is the file. It is a useful piece of information, such as a digital photo, saved e-mail message, or Web page. Dealing with photos, e-mails, and Web pages is easier than the details of disks, such as the floppy disk described above. The job of the operating system is to create good abstractions and then implement and manage the abstract objects thus created. Abstractions are one of the keys to understanding operating systems. This point is so important that it is worth repeating in different words. Real processors, memories, disks, and other devices are very complicated and present difficult, awkward, idiosyncratic, and inconsistent interfaces to the people who have to write software to use them. Sometimes this is due to the need for backward compatibility with older hardware, sometimes due to a desire to save money, but sometimes the hardware designers do not realize (or care) how much trouble they are causing for the software. One of the major tasks of the operating system is to hide the hardware and present programs with nice, clean, elegant, consistent, abstractions to work with instead.

Operating systems turn the ugly into the beautiful using abstraction concept.

It should be noted that the operating system's real customers are the application programs (via the application programmers, of course). They are the ones who deal directly with the operating system and its abstractions. In contrast, end users deal with the abstractions provided by the user interface, either a commandline shell or a graphical interface. While the abstractions at the user interface may be similar to the ones provided by the operating system, this is not always the case. To make this point clearer, consider the normal Windows desktop and the line-oriented command prompt. Both are programs running on the Windows operating system and use the abstractions Windows provides, but they offer very different user interfaces. Similarly, a Linux user running Gnome or KDE sees a very different interface than a Linux user working directly on top of the underlying (text-oriented) X Window System, but the underlying operating system abstractions are the same in both cases.That is a large and important subject, but one only peripherally related to operating systems.

Second case: Resource Manager
Modern computers consist of processors, memories, timers, disks, mice, network interfaces, printers, and a wide variety of other devices. The concept of an operating system as primarily providing abstractions to application programs is a top-down view. An alternative, bottom-up, view holds that the operating system is there to manage all the pieces of a complex system. In the alternative view, the job of the operating system is to provide for an orderly and controlled allocation of the processors, memories, and I/0 devices among the various programs competing for them.

Modem operating systems allow multiple programs to run at the same time. Imagine what would happen if three programs running on some computer all tried to print their output simultaneously on the same printer. The first few lines of printout might be from program 1, the next few from program 2, then some from program 3, and so forth. The result would be chaos. The operating system can bring order to the potential chaos by buffering all the output destined for the printer on the disk. When one program is finished, the operating system can then copy its output from the disk file where it has been stored for the printer, while at the same time the other program can continue generating more output, oblivious to the fact that the output is not really going to the printer (yet). When a computer (or network) has multiple users, the need for managing and protecting the memory, 110 devices, and other resources is even greater, since the users might otherwise interfere with one another. In addition, users often need to share not only hardware, but information (files, databases, etc.) as well.

In short, this view of the operating system holds that its primary task is to keep track of which programs are using which resource, to grant resource requests, to account for usage, and to mediate conflicting requests from different programs and users.

Resource management includes multiplexing (sharing) resources in two different ways: in time and in space. When a resource is time multiplexed, different programs or users take turns using it. First one of them gets to use the resource, then another, and so on. For example, with only one CPU and multiple programs that want to run on it, the operating system first allocates the CPU to one program, then, after it has run long enough, another one gets to use the CPU, then another, and then eventually the first one again. Determining how the resource is time multiplexed- who goes next and for how long-is the task of the operating system. Another example of time multiplexing is sharing the printer. When multiple print jobs are queued up for printing on a single printer, a decision has to be made about which one is to be printed next.

Tuesday, May 8, 2012

What design choices have to be made when integrating COTS products to create a COTS-solution system?


What design choices have to be made when integrating COTS products to create a COTS-solution system?
Ans: To develop systems using COTS products, you have to make a number of design choices:
1. Which COTS products offer the most appropriate functionality? Typically, there will be several COTS products available, which can be combined in different ways. If you don’t already have experience with a COTS product, it can be difficult to decide which product is the most suitable.
2. How will data be exchanged? Different products normally use unique data structures and formats. You have to write adaptors that convert from one representation to another. These adaptors are run-time systems that operate alongside the COTS products.
3. What features of a product will actually be used? COTS products may include more functionality than you need and functionality may be duplicated across different products. You have to decide which features in what product are most appropriate for your requirements. If possible, you should also deny access to unused functionality because this can interfere with normal system operation. The failure of the first flight of the Ariane 5 rocket was a consequence of a failure in an inertial navigation system that was reused from the Ariane 4 system. However, the functionality that failed was not actually
required in Ariane 5.

What is an ERP system?


What is an ERP system?
Ans: At a larger scale, an Enterprise Resource Planning (ERP) system may support all of the manufacturing, ordering, and customer relationship management activities in a large company.
ERP systems, such as those produced by SAP and BEA, are large-scale integrated systems designed to support business practices such as ordering and invoicing, inventory management, and manufacturing scheduling. The configuration process for these systems involves gathering detailed information about the customer’s business and business processes, and embedding this in a configuration database. This often requires detailed knowledge of configuration notations and tools and is usually carried out by consultants working alongside system customers. ERP systems are used in almost all large companies to support some or all of their functions. They are, therefore, a very widely used form of software reuse.

What are the main benefits of COTS reuse?


What are the main benefits of COTS reuse?
Ans: The main benefits of COTS reuse are:
1. As with other types of reuse, more rapid deployment of a reliable system may be possible.
2. It is possible to see what functionality is provided by the applications and so it is easier to judge whether or not they are likely to be suitable. Other companies may already use the applications so experience of the systems is available.
3. Some development risks are avoided by using existing software. However, this approach has its own risks, as I discuss below.
4. Businesses can focus on their core activity without having to devote a lot of resources to IT systems development.
            5. As operating platforms evolve, technology updates may be simplified as these are the responsibility of the COTS product vendor rather than the customer.

What are the process steps involved in creating a new member of a software product line?


What are the process steps involved in creating a new member of a software product line?
Ans: The process steps involved in extending a software product line to create a new application are as follows:
1. Elicit stakeholder requirements: You may start with a normal requirements engineering process. However, because a system already exists, you will need to demonstrate the system and have stakeholders experiment with it, expressing their requirements as modifications to the functions provided.
2. Select the existing system that is the closest fit to the requirements: When creating a new member of a product line, you may start with the nearest product instance. The requirements are analyzed and the family member that is the closest fit is chosen for modification.
3. Renegotiate requirements: As more details of required changes emerge and the project is planned, there may be some requirements renegotiation to minimize the changes that are needed.
4. Adapt existing system: New modules are developed for the existing system and existing system modules are adapted to meet the new requirements.
            5. Deliver new family member: The new instance of the product line is delivered to the customer. At this stage, you should document its key features so that it may be used as a basis for other system developments in the future.

List 4 types of specialization of software product lines?


List 4 types of specialization of software product lines?
Ans: Various types of specialization of a software product line may be developed:
1. Platform specialization: Versions of the application are developed for different platforms. For example, versions of the application may exist for Windows, Mac OS, and Linux platforms. In this case, the functionality of the application is normally unchanged; only those components that interface with the hardware and operating system are modified.
2. Environment specialization: Versions of the application are created to handle particular operating environments and peripheral devices. For example, a system for the emergency services may exist in different versions, depending on the vehicle communications system. In this case, the system components are changed to reflect the functionality of the communications equipment used.
3. Functional specialization: Versions of the application are created for specific customers who have different requirements. For example, a library automation system may be modified depending on whether it is used in a public library, a reference library, or a university library. In this case, components that implement functionality may be modified and new components added to the system.
4. Process specialization: The system is adapted to cope with specific business processes. For example, an ordering system may be adapted to cope with a centralized ordering process in one company and a distributed process in another.

What features are supported by most web application frameworks?


What features are supported by most web application frameworks?
Ans: Most web application frameworks support the following features:
1. Security WAFs may include classes to help implement user authentication (login) and access control to ensure that users can only access permitted functionality in the system.
2. Dynamic web pages Classes are provided to help you define web page templates and to populate these dynamically with specific data from the system database.
3. Database support Frameworks don’t usually include a database but rather assume that a separate database, such as MySQL, will be used. The framework may provide classes that provide an abstract interface to different databases.
4. Session management Classes to create and manage sessions (a number of interactions with the system by a user) are usually part of a WAF.
5. User interaction Most web frameworks now provide AJAX support, which allows more interactive web pages to be created.

What are the three classes of application framework discussed by Fayed and Schmidt?


What are the three classes of application framework discussed by Fayed and Schmidt?
Ans: Fayad and Schmidt discuss three classes of frameworks:
1. System infrastructure frameworks: These frameworks support the development of system infrastructures such as communications, user interfaces, and compilers.
2. Middleware integration frameworks: These consist of a set of standards and associated object classes that support component communication and information exchange. Examples of this type of framework include Microsoft’s .NET and Enterprise Java Beans (EJB). These frameworks provide support for standardized component models, as discussed in Chapter 17.
3. Enterprise application frameworks: These are concerned with specific application domains such as telecommunications or financial systems. These embed application domain knowledge and support the development of end-user applications.

What key factors should be considered when considering the most appropriate type of reuse?


What key factors should be considered when considering the most appropriate type of reuse?
Ans: Key factors that you should consider when planning reuse are:
1. The development schedule for the software: If the software has to be developed quickly, you should try to reuse off-the-shelf systems rather than individual components. These are large-grain reusable assets. Although the fit to requirements may be imperfect, this approach minimizes the amount of development required.
2. The expected software lifetime: If you are developing a long-lifetime system, you should focus on the maintainability of the system. You should not just think about the immediate benefits of reuse but also of the long-term implications. Over its lifetime, you will have to adapt the system to new requirements, which will mean making changes to parts of the system. If you do not have access to the source code, you may prefer to avoid off-the-shelf components and systems from external suppliers; suppliers may not be able to continue support for the reused software.
3. The background, skills, and experience of the development team: All reuse technologies are fairly complex and you need quite a lot of time to understand and use them effectively. Therefore, if the development team has skills in a particular area, this is probably where you should focus.
4. The criticality of the software and its non-functional requirements: For a critical system that has to be certified by an external regulator, you may have to create a dependability case for the system. This is difficult if you don’t have access to the source code of the software. If your software has stringent performance requirements, it may be impossible to use strategies such as generator-based reuse, where you generate the code from a reusable domain specific representation of a system. These systems often generate relatively inefficient code.
5. The application domain: In some application domains, such as manufacturing and medical information systems, there are several generic products that may be reused by configuring them to a local situation. If you are working in such a domain, you should always consider these as an option.
6. The platform on which the system will run: Some components models, such as .NET, are specific to Microsoft platforms. Similarly, generic application systems may be platform-specific and you may only be able to reuse these if your system is designed for the same platform.

What are the main problems with software reuse?


What are the main problems with software reuse?
Ans:     Increased maintenance costs: If the source code of a reused software system or component is not available, then maintenance costs may be higher because the reused elements of the system may become increasingly incompatible with system changes.
Lack of tool support: Some software tools do not support development with reuse. It may be difficult or impossible to integrate these tools with a component library system. The software process assumed by these tools may not take reuse into account. This is particularly true for tools that support embedded systems engineering, less so for object-oriented development tools.
Not-invented-here syndrome: Some software engineers prefer to rewrite components because they believe they can improve on them. This is partly to do with trust and partly to do with the fact that writing original software is seen as more challenging than reusing other people’s software.
Creating, maintaining, and using a component library: Populating a reusable component library and ensuring the software developers can use this library can be expensive. Development processes have to be adapted to ensure that the library is used.
Finding, understanding, and adapting reusable components: Software components have to be discovered in a library, understood and, sometimes, adapted to work in a new environment. Engineers must be reasonably confident of finding a component in the library before they include a component search as part of their normal development process.

List the main benefits of software reuse.


List the main benefits of software reuse.
Ans:     Increased dependability: Reused software, which has been tried and tested in working systems, should be more dependable than new software. Its design and implementation faults should have been found and fixed.
Reduced process risk: The cost of existing software is already known, whereas the costs of development are always a matter of judgment. This is an important factor for project management because it reduces the margin of error in project cost estimation. This is particularly true when relatively large software components such as subsystems are reused.
Effective use of specialists: Instead of doing the same work over and over again, application specialists can develop reusable software that encapsulates their knowledge.
Standards compliance: Some standards, such as user interface standards, can be implemented as a set of reusable components. For example, if menus in a user interface are implemented using reusable components, all applications present the same menu formats to users. The use of standard user interfaces improves dependability because users make fewer mistakes when presented with a familiar interface.
Accelerated development: Bringing a system to market as early as possible is often more important than overall development costs. Reusing software can speed up system.

Tuesday, April 24, 2012

Programming Pointers Definition C/C++ (Learn what are pointers? How defined and used using sample example pointer code in C++)

Pointers Definition: A pointer is a data type recognized by C++ and C, but not by Java. A variable of data type pointer contains an address of some other data element stored in data memory (RAM), e.g., the address of the value stored in some other variable. The pointer variable itself is also stored at some address in data memory.


Diagram to learn programming pointers: 

Pointers in different computer programming languages: 


Pointers in C++/C: A pointer variable contains the address of other data elements. The values stored at the address can be changed, copied, etc., using only the address. Advantage of pointers in C/C++ is that programmers can directly access memory locations of the variables assigned while programming application programs either for embedded systems or operating system programs. Pointers should be used very carefully while programming your application in C/C++ since mirror error in pointer can terminate your whole application.

Pointers in Java: Java programmer does not have access to pointers. Pointers are used implicitly by the Java compiler/interpreter. Actually used more frequently by the Java compiler/interpreter than by the either the C++ or C compiler. Explicit manipulation of addresses/pointers by the Java programmer is forbidden. 

Now lets simply understand how pointers are defined and used in C++ using simple example for better understanding pointers for practical purposes:
STEP 1: float A;
1. First of all, the data type of variable A is float.
2. The variable name A is for human/programmer use only. The compiler converts the variable name into an address/pointer that is used by the compiled code to access the value stored at that address.
3. The variable name is converted by the compiler into an address in data memory.
4. The address that is synonymous with to the variable name A contains the value that has been assigned to that variable.
5. Normally the code that manipulates the address that corresponds to the variable A is hidden from the programmer. 6. If desired by the programmer that address can be accessed, again it is only possible in C and C++ but not in JAVA. Variable address can be accessed using:
a. A reference to the variable A, as in &A.
b. A pointer to A (explained below).

STEP 2: float* PtrToA;
1. The notation float* defines the data type of pointer-to-float.
2. The variable name which follows is, then, the name of a variable which holds a value which is the address of some floating point value.
3. Alternate notation: float *PtrToA;

STEP 3: A = 3.1415;
1. Standard assignment statement.
2. The constant value 3.1415 is stored at the address in RAM that corresponds to the variable A.


STEP 4: PtrToA = &A;
1. A slightly different assignment statement.
2. The notation &A designates the address of the variable A.
3. Therefore: PtrToA = &A; causes the address of the variable A to be loaded into the address in RAM that corresponds to the pointer variable PtrToA.

In the end, lets program in C++ what we have explained above about pointers usage to see the actual results in programming how pointers are defined inside computer memory and how pointers are used inside the computer programming.

Samle example Code:
#include <iostream>
using namespace std; 
void main() 
{
float A; // declaration of a floating point variable 
// allocates four bytes of RAM and attaches // the memory to the program. 
          float* PtrToA; // declaration of a variable that will hold the
// address of a floating point number. 
          A = 3.1415; // Assign a value to the floating point variable, i.e., store a value at the address
// in RAM that is synonymous with the  variable name. 
          PtrToA = &A; // The value assigned to the pointer variable is the address of the floating point variable
          cout << endl << "The value of A is " << A << " while the address of A is " << PtrToA << endl << "                and the value stored at the address " << PtrToA << " is " << *PtrToA << endl;
         *PtrToA = 89.526;
          cout << endl << "The value of A is " << A << " while the address of A is " << PtrToA << endl << " and the value stored at the address " << PtrToA << " is " << *PtrToA << endl;


The output of the above sample code to understand pointers would be:


The value of A is 3.1415 while the address of A is 0012FF7C and the value stored at the address 0012FF7C is 3.1415 
The value of A is 89.526 while the address of A is 0012FF7C and the value stored at the address 0012FF7C is 89.526

Wednesday, April 18, 2012

FSM VHDL Lab Code for Thunderbird Turn Signal circuit design (FPGA Digital Systems Project Explanation)


Using Thunderbird Turn Signal digital circuit lab, you can learn how the logic of finite state machine is implemented in real life embedded world for example in this case, 1965 Ford Thunderbird. FSM's contributes a lot more functionality to the world of Digital Systems

SO What is FSM (finite-state machine): A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible transition states from each current state, and the triggering condition for each transition.

Now after getting familiar with FSM, lets practice programming it in VHDL language using Thunderbird Turn Signal fsm design circuit lab.

Project specification: The tail lights of a 1965 Ford Thunderbird is shown below. There are three lights on each side that operate in sequence to indicate the direction of a turn. There are three flashing sequence: left turn, right turn, and hazard.


The left-turn sequence is:



The right-turn sequence is similar and represents a “mirror” sequence of the left-turn pattern. In the hazard sequence, the six lights flash on and off alternatively. In all sequences, we assume that each pattern stays for 300 ms.

A simple FSM can be constructed to control the tail light operation. The input and output of the thunderbird turn signal lab are as follows:

Input:
 clk: 50 MHz clock signal from the DE1 board.
 reset
 tick: 1-bit 300ms “tick” signal. It is asserted for one clock cycle every 300 ms.
 left: 1-bit left-turn signal.
 right: 1-bit right-turn signal.
 haz: 1-bit hazard signal.

Output:
 light: 6-bit light signal.

The Thunderbird Turn Signal digital design circuit lab system operates as follows:
11.> Anytime haz is asserted, the FSM enters the hazard sequence immediately. If the FSM currently in the middle of a left- or right-turn, sequence, the sequence will be aborted.

22.> When haz is not asserted and left is asserted and, the FSM goes through the complete left-turn sequence. This means that the lights should go through a complete left-turn sequence even if left is de asserted sometime in the middle of the sequence or if right is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

33.> When haz is not asserted and right is asserted and, the FSM goes through the complete right-turn sequence. This means that the lights should go through a complete right-turn sequence even if right is de-asserted sometime in the middle of the sequence or if left is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

44.> We assume that left and right will never be asserted simultaneously.


Design Procedures: We can divide this circuit into two segments: 

Counter: generate a one-clock pulse (tick) every 300 ms. 
=>> I have explained how to achieve counter functionality in previous post(you can find them there: digital systems labs). 

FSM: 
=>> Convert the state diagram to an ASM chart following the notations used in the text. Once done with state diagrams, design the FSM as an independent VHDL module.  The entity declaration of this design is    
entity tbird_fsm is
   port(

   clk, reset: std_logic;

   tick, left, right, haz: std_logic;

   light: out std_logic_vector(5 downto 0);
    );
  END tbird_fsm;

After that we will also need to derive the architecture body which will be added below in whole program code. 

Thunderbird lab VHDL code for implementing tail light FSM digital systems circuit:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lights is
   port(
      clk, reset: in std_logic;
      l, r, h: in std_logic;
      light: out std_logic_vector(5 downto 0)
   );
end lights;
architecture arch of lights is
   constant DVSR: integer:=5000000;
   signal ms_reg, ms_next: unsigned(22 downto 0);
 
   type eg_state_type is (s0, sh1, sh2, sl1, sl2, sl3, sr1, sr2, sr3);
   signal state_reg, state_next: eg_state_type;
begin
  process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
-- d0_reg <= d0_next;
      end if;
   end process;
ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
 -- state register
   process(reset,clk,ms_reg,state_reg)
   begin
      if (reset='1') then
         state_reg <= s0;
      elsif (clk='1' and clk'event) then
if (ms_reg=DVSR) then
state_reg <= state_next;
      end if;
end if;
   end process;
   -- next-state logic
   process(state_reg, l, r, h, clk)
   begin
--if tick='1' then
      case state_reg is
        when s0=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sh1=>
state_next <= sh2;
when sh2=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sl1=>
if (h='1') then state_next <= sh1;
else state_next <= sl2;
end if;
when sl2=>
if (h='1') then state_next <= sh1;
else state_next <= sl3;
end if;
when sl3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sr1=>
if (h='1') then state_next <= sh1;
else state_next <= sr2;
end if;
when sr2=>
if (h='1') then state_next <= sh1;
else state_next <= sr3;
end if;
when sr3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
      end case;
--end if;
end process;
   -- Moore output logic
   process(state_reg)
   begin
      case state_reg is
         when s0 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sh1 =>
-- if tick='1' then
            light <= "111111";
-- end if;
         when sh2 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sl1 =>
-- if tick='1' then
            light <= "001000";
-- end if;
         when sl2 =>
-- if tick='1' then
            light <= "011000";
-- end if; when sl3 =>
-- if tick='1' then
            light <= "111000";
-- end if;
         when sr1 =>
-- if tick='1' then
            light <= "000100";
-- end if; when sr2 =>
-- if tick='1' then
            light <= "000110";
-- end if;
when sr3 =>
-- if tick='1' then
            light <= "000111";
-- end if;
      end case;
   end process;
end arch;



   
Then obviously compile the design and perform simulation to verify its operation. I used EP2C20F484C8 Cyclone ii FPGA Starter board for implementation of Thunderbird Turn Signal FSM digital circuit design.

Implementation and testing:
You will use the 50MHz oscillator for clock and 4 switches for the reset signal and three control signals. You could use any FPGA board but I have compiled and tested the code on Altera provided FPGA board. I have posted below the pin assignments I used for my EP2C20F484C8 Cyclone ii FPGA Starter board:
From To Assignment Name Value Enabled
     reset Location PIN_L22 Yes
     h Location PIN_L21 Yes
     r Location PIN_M22 Yes
     l Location PIN_V12 Yes
     clk Location PIN_L1 Yes
light[0] Location PIN_R20 Yes
light[1] Location PIN_R19 Yes
light[2] Location PIN_U19 Yes
light[3] Location PIN_Y19 Yes
light[4] Location PIN_T18 Yes
light[5] Location PIN_V19 Yes

Tuesday, April 3, 2012

Rotating LED VHDL Lab Code With Intermediate-Sized Sequential Circuit Project Design and Procedures

Rotating LED is an intermediate-sized sequential circuit. Rotating LED lab will utilize seven-segment LED and clock functionality. VHDL language is used to implement this rotating LED logic on Altera DE1 FPGA device using  Altera Quartus design suite.

Project specification: In a seven-segment LED display, a square pattern can be created by enabling the a, b, f, and g segments or the c, d, e, and g segments. We want to design a circuit that circulates the square patterns in the four-digit seven-segment LED display. The circulating pattern could either be clockwise or counter-clockwise depending on the user input. The clockwise circulating pattern is shown above, just to give you an idea how we want to implement our rotating LED circuit logic. The control signals of the circuit can specify the rotation speed, the direction of rotation (i.e., clockwise or counterclockwise), and pause the operation. The rotating LED circuit design must be synchronous. We will use 4 switches for the control signals and 50MHz oscillator for clock from DE1 Altera FPGA board. The input and output signals for rotating LED logic circuit will be as follows:

Inputs:
• clk: 50 MHz clock signal from the DE1 board.
• pa: 1-bit enable signal. The circulation pauses when it is 1.
• cw: 1-bit direction signal. The pattern circulates clockwise when it is 1 and counter
clockwise when it is 0.
• sp: 2-bit speed control:
• 00: each pattern stays 20 ms
• 01: each pattern stays 40 ms
• 10: each pattern stays 80 ms
• 11: each pattern stays 160 ms

Output:
• Four seven-segment LED displays.



Design Procedures: We can divide rotating LED circuit into four segments and finally we can add up a wrapping VHDL code to instantiate all the modules. Lets first go through each module required to do the rotating LED circuit lab with the VHDL code provided:

Counter 1: generate a one-clock pulse (tick1) every 10 ms.


VHDL module Code to generate one clock pulse every 10 ms:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_1 is
   port(
      clk: in std_logic;
      tick1: out std_logic
   );
end counter_1;
architecture arch of counter_1 is
   constant DVSR: integer:=500000;
   signal ms_reg, ms_next: unsigned(18 downto 0);
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01(10ms) sec tick generator: mod-500000
   ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
   tick1 <= '1' when ms_reg=DVSR else '0';
end arch;   



Counter 2: utilizes tick1 pulse and generates a one-clock pulse (tick2) every 20 ms, 40 ms, 80 ms or 160 ms based on the sp input signal.

VHDL module Code to control the speed of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_2 is
   port(
      clk: in std_logic;
tick1: in std_logic;
sp: in std_logic_vector(1 downto 0);
      tick2: out std_logic
   );
end counter_2;
architecture arch of counter_2 is
   signal d1_reg, d0_reg: unsigned(3 downto 0);
   signal d1_next, d0_next: unsigned(3 downto 0);
   signal d1_en, d0_en: std_logic;
   signal d0_tick, tick_20ms, tick_40ms, tick_80ms, tick_160ms: std_logic;
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         d1_reg <= d1_next;
         d0_reg <= d0_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01 sec counter
   d0_en <= '1' when tick1='1' else '0';
   d0_next <=
      "0000" when (d0_en='1' and d0_reg=15) else
      d0_reg + 1 when d0_en='1' else
      d0_reg;
    tick_20ms <= '1' when d0_reg=2 else '0';
tick_40ms <= '1' when d0_reg=4 else '0';
tick_80ms <= '1' when d0_reg=8 else '0';
d0_tick <= '1' when d0_reg=9 else '0';
   -- .1 sec counter
   d1_en <= '1' when tick1='1' and d0_tick='1' else '0';
   d1_next <=
      "0000" when (d1_en='1' and d1_reg=9) else
      d1_reg + 1 when d1_en='1' else
      d1_reg;
   tick_160ms <= '1' when (d1_reg=1 and d0_reg=6) else '0';
   -- output logic
with sp select
      tick2 <=   tick_20ms when "00",
                 tick_40ms when "01",
                 tick_80ms when "10",
                 tick_160ms when others;
end arch;




Counter 3: mod-8 counter that utilizes tick2 pulse and can pause, count up and count down.

VHDL module Code for mod 8 counter to control the direction of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_3 is
   generic(
      N: integer := 3;     -- number of bits
      M: integer := 8      -- mod-M
  );
   port(
      clk: in std_logic;
      tick2, cw, pa: in std_logic;
      q: out std_logic_vector(N-1 downto 0)
   );
end counter_3;
architecture arch of counter_3 is
   signal r_regf, r_reg1, r_reg2: unsigned(N-1 downto 0);
   signal r_nextf, r_next1, r_next2: unsigned(N-1 downto 0);
begin
   -- register
   process(clk,pa)
   begin
      if (clk'event and clk='1' and tick2='1' and pa='0') then
         r_regf <= r_nextf;
         r_reg1 <= r_next1;
         r_reg2 <= r_next2;
end if;
   end process;
   -- next-state logic
r_next1 <= (others=>'0') when r_reg1=(M-1) else
             r_reg1 + 1;
r_next2 <= (others=>'1') when r_reg2=(0) else
             r_reg2 - 1;
r_nextf <= r_next1 when(cw='1') else
 r_next2;
-- output logic
   q <= std_logic_vector(r_regf);
end arch;



Decoding Circuit: A decoding circuit that generates the desired LED patterns.

VHDL module code for decoding rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
entity decoder_rotatingLED is
port
(
input: in std_logic_vector(2 downto 0);
en: out std_logic_vector(27 downto 0)
);
end decoder_rotatingLED;
architecture arch of decoder_rotatingLED is
begin
process(input)
begin
case input  is
            when "000" =>   en <= "0011100111111111111111111111";
            when "001" =>   en <= "1111111001110011111111111111";
            when "010" =>   en <= "1111111111111100111001111111";
            when "011" =>   en <= "1111111111111111111110011100";
            when "100" =>   en <= "1111111111111111111110100011";
            when "101" =>   en <= "1111111111111101000111111111";
            when "110" =>   en <= "1111111010001111111111111111";
            when "111" =>   en <= "0100011111111111111111111111";
end case;
end process;
end arch;
Final Wrapping up circuit for rotating LED circuit which will instantiate all the modules defined above(counter1, counter2, counter3, decoding circuit). In Altera Quartus design suite, this final rotatingLED VHDL module will be set as top level entity declaration before compiling.

VHDL module Code for rotatingLED is:


library ieee;
use ieee.std_logic_1164.all;
entity rotatingLED is
port
(
final_clk: in std_logic;
final_pa, final_cw: in std_logic;
final_sp: in std_logic_vector(1 downto 0);
hex3, hex2, hex1, hex0: out std_logic_vector(6 downto 0)
);
end rotatingLED;
architecture arch of rotatingLED is
signal temp0, temp1: std_logic;
signal temp2: std_logic_vector(2 downto 0);
signal cycle: std_logic_vector(27 downto 0);
begin
c1_unit: entity work.counter_1(arch)
port map(clk=>final_clk, tick1=>temp0);
c2_unit: entity work.counter_2(arch)
port map(clk=>final_clk, tick1=>temp0, sp=>final_sp, tick2=>temp1);
c3_unit: entity work.counter_3(arch)
port map(clk=>final_clk, tick2=>temp1, pa=>final_pa, cw=>final_cw, q=>temp2);
decoder_rotatingLED_unit: entity work.decoder_rotatingLED(arch)
port map(input=>temp2, en=>cycle);
hex3 <= cycle(27 downto 21);
hex2 <= cycle(20 downto 14);
hex1 <= cycle(13 downto 7);
hex0 <= cycle(6 downto 0);
end arch;

We will also do the pin assignment for this rotating LED circuit lab as follows:
From To Assignment Name Value Enabled
     final_pa Location PIN_L22 Yes
     final_cw Location PIN_L21 Yes
     final_sp[0] Location PIN_M22 Yes
     final_sp[1] Location PIN_V12 Yes
     final_clk Location PIN_L1 Yes
hex0[0] Location PIN_J2 Yes
hex0[1] Location PIN_J1 Yes
hex0[2] Location PIN_H2 Yes
hex0[3] Location PIN_H1 Yes
hex0[4] Location PIN_F2 Yes
hex0[5] Location PIN_F1 Yes
hex0[6] Location PIN_E2 Yes
hex1[0] Location PIN_E1 Yes
hex1[1] Location PIN_H6 Yes
hex1[2] Location PIN_H5 Yes
hex1[3] Location PIN_H4 Yes
hex1[4] Location PIN_G3 Yes
hex1[5] Location PIN_D2 Yes
hex1[6] Location PIN_D1 Yes
hex2[0] Location PIN_G5 Yes
hex2[1] Location PIN_G6 Yes
hex2[2] Location PIN_C2 Yes
hex2[3] Location PIN_C1 Yes
hex2[4] Location PIN_E3 Yes
hex2[5] Location PIN_E4 Yes
hex2[6] Location PIN_D3 Yes
hex3[0] Location PIN_F4 Yes
hex3[1] Location PIN_D5 Yes
hex3[2] Location PIN_D6 Yes
hex3[3] Location PIN_J4 Yes
hex3[4] Location PIN_L8 Yes
hex3[5] Location PIN_F3 Yes
hex3[6] Location PIN_D4 Yes

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