Majority Circuit VHDL Code (a circuit that counts 4 votes and displays the results)

Project specification:
We want to design a circuit that counts 4 votes and displays the results. Only VHDL logical operators (i.e., and, or, not, and xor) can be used in VHDL code and no process is allowed.

Our input and outputs should be as follows:

1. v: 4-bit inputs representing 4 votes, with 1 for yes and 0 for no..output
2. fail: 1-bit output. It is asserted when the motion fails (i.e., less than two 1’s).
3. tie: 1-bit output. It is asserted when the vote is a tie (i.e., two 1’s and two 0’s).
4. pass: 1-bit output. It is asserted when there is a majority (i.e., three or four 1’s).

Majority Circuit VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity majority_circuit is
port(
v: in std_logic_vector(3 downto 0);
fail, tie, pass: out std_logic
);
end majority_circuit;
architecture decisionMaker of majority_circuit is
signal p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13: std_logic;
begin
fail <= p0 or p1 or p2 or p3;
p0 <= ((not v(3)) and (not v(2)) and (not v(0)));
p1 <= ((not v(3)) and (not v(2)) and (not v(1)));
p2 <= ((not v(3)) and (not v(1)) and (not v(0)));
p3 <= ((not v(2)) and (not v(1)) and (not v(0)));
tie <= p4 or p5 or p6 or p7 or p8 or p9;
p4 <= ((not v(3)) and (not v(2)) and v(1) and v(0));
p5 <= ((not v(3)) and v(2) and (not v(1)) and v(0));
p6 <= ((not v(3)) and v(2) and v(1) and (not v(0)));
p7 <= (v(3) and (not v(2)) and (not v(1)) and v(0));
p8 <= (v(3) and (not v(2)) and v(1) and (not v(0)));
p9 <= (v(3) and v(2) and (not v(1)) and (not v(0)));
pass <= p10 or p11 or p12 or p13;
p10 <= (v(3) and v(2) and v(0));
p11 <= (v(2) and v(1) and v(0));
p12 <= (v(3) and v(1) and v(0));
p13 <= (v(3) and v(2) and v(1));
end decisionMaker;