Barrel Shifter VHDL Code with diagram to learn

Barrel Shifter: Rotates 8-bit input by a specific amount.

Problem with large input (e.g., 32 bits)
– Large multiplexing structure
– Lengthy code
– Better alternative

Barrel Shifter VHDL Code:
library ieee;
use ieee.std_logic_1164.all;
entity barrel_shifter is
   port(
      a: in std_logic_vector(7 downto 0);
      amt: in std_logic_vector(2 downto 0);
      y: out std_logic_vector(7 downto 0)
   );
end barrel_shifter ;
architecture sel_arch of barrel_shifter is
begin
   with amt select
      y<= a                             when "000",
          a(0) & a(7 downto 1)          when "001",
          a(1 downto 0) & a(7 downto 2) when "010",
          a(2 downto 0) & a(7 downto 3) when "011",
          a(3 downto 0) & a(7 downto 4) when "100",
          a(4 downto 0) & a(7 downto 5) when "101",
          a(5 downto 0) & a(7 downto 6) when "110",
          a(6 downto 0) & a(7) when others; -- 111
end sel_arch;

Read More

FSM VHDL Lab Code for Thunderbird Turn Signal circuit design (FPGA Digital Systems Project Explanation)

Using Thunderbird Turn Signal digital circuit lab, you can learn how the logic of finite state machine is implemented in real life embedded world for example in this case, 1965 Ford Thunderbird. FSM's contributes a lot more functionality to the world of Digital Systems. 

SO What is FSM (finite-state machine): A finite-state machine (FSM) or finite-state automaton (plural: automata), or simply a state machine, is a mathematical model used to design computer programs and digital logic circuits. It is conceived as an abstract machine that can be in one of a finite number of states. The machine is in only one state at a time; the state it is in at any given time is called the current state. It can change from one state to another when initiated by a triggering event or condition, this is called a transition. A particular FSM is defined by a list of the possible transition states from each current state, and the triggering condition for each transition.

Now after getting familiar with FSM, lets practice programming it in VHDL language using Thunderbird Turn Signal fsm design circuit lab.

Project specification: The tail lights of a 1965 Ford Thunderbird is shown below. There are three lights on each side that operate in sequence to indicate the direction of a turn. There are three flashing sequence: left turn, right turn, and hazard.

The left-turn sequence is:

The right-turn sequence is similar and represents a “mirror” sequence of the left-turn pattern. In the hazard sequence, the six lights flash on and off alternatively. In all sequences, we assume that each pattern stays for 300 ms.

A simple FSM can be constructed to control the tail light operation. The input and output of the thunderbird turn signal lab are as follows:

Input:

 clk: 50 MHz clock signal from the DE1 board.

 reset

 tick: 1-bit 300ms “tick” signal. It is asserted for one clock cycle every 300 ms.

 left: 1-bit left-turn signal.

 right: 1-bit right-turn signal.

 haz: 1-bit hazard signal.

Output:

 light: 6-bit light signal.

The Thunderbird Turn Signal digital design circuit lab system operates as follows:

11.> Anytime haz is asserted, the FSM enters the hazard sequence immediately. If the FSM currently in the middle of a left- or right-turn, sequence, the sequence will be aborted.

22.> When haz is not asserted and left is asserted and, the FSM goes through the complete left-turn sequence. This means that the lights should go through a complete left-turn sequence even if left is de asserted sometime in the middle of the sequence or if right is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

33.> When haz is not asserted and right is asserted and, the FSM goes through the complete right-turn sequence. This means that the lights should go through a complete right-turn sequence even if right is de-asserted sometime in the middle of the sequence or if left is asserted in the middle of a sequence. However, the FSM enters the hazard sequence if haz is asserted.

44.> We assume that left and right will never be asserted simultaneously.

Design Procedures: We can divide this circuit into two segments: 

Counter: generate a one-clock pulse (tick) every 300 ms. 

=>> I have explained how to achieve counter functionality in previous post(you can find them there: digital systems labs). 

FSM: 

=>> Convert the state diagram to an ASM chart following the notations used in the text. Once done with state diagrams, design the FSM as an independent VHDL module.  The entity declaration of this design is    

entity tbird_fsm is

   port(

   clk, reset: std_logic;

   tick, left, right, haz: std_logic;

   light: out std_logic_vector(5 downto 0);

    );

  END tbird_fsm;

After that we will also need to derive the architecture body which will be added below in whole program code. 

Thunderbird lab VHDL code for implementing tail light FSM digital systems circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity lights is
   port(
      clk, reset: in std_logic;
      l, r, h: in std_logic;
      light: out std_logic_vector(5 downto 0)
   );
end lights;
architecture arch of lights is
   constant DVSR: integer:=5000000;
   signal ms_reg, ms_next: unsigned(22 downto 0);
 
   type eg_state_type is (s0, sh1, sh2, sl1, sl2, sl3, sr1, sr2, sr3);
   signal state_reg, state_next: eg_state_type;
begin
  process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
-- d0_reg <= d0_next;
      end if;
   end process;
ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
 -- state register
   process(reset,clk,ms_reg,state_reg)
   begin
      if (reset='1') then
         state_reg <= s0;
      elsif (clk='1' and clk'event) then
if (ms_reg=DVSR) then
state_reg <= state_next;
      end if;
end if;
   end process;
   -- next-state logic
   process(state_reg, l, r, h, clk)
   begin
--if tick='1' then
      case state_reg is
        when s0=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sh1=>
state_next <= sh2;
when sh2=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sl1=>
if (h='1') then state_next <= sh1;
else state_next <= sl2;
end if;
when sl2=>
if (h='1') then state_next <= sh1;
else state_next <= sl3;
end if;
when sl3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
when sr1=>
if (h='1') then state_next <= sh1;
else state_next <= sr2;
end if;
when sr2=>
if (h='1') then state_next <= sh1;
else state_next <= sr3;
end if;
when sr3=>
if (h='1') then state_next <= sh1;
elsif (l='1') then state_next <= sl1;
elsif (r='1') then state_next <=sr1;
else state_next <= s0;
end if;
      end case;
--end if;
end process;
   -- Moore output logic
   process(state_reg)
   begin
      case state_reg is
         when s0 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sh1 =>
-- if tick='1' then
            light <= "111111";
-- end if;
         when sh2 =>
-- if tick='1' then
            light <= "000000";
-- end if; when sl1 =>
-- if tick='1' then
            light <= "001000";
-- end if;
         when sl2 =>
-- if tick='1' then
            light <= "011000";
-- end if; when sl3 =>
-- if tick='1' then
            light <= "111000";
-- end if;
         when sr1 =>
-- if tick='1' then
            light <= "000100";
-- end if; when sr2 =>
-- if tick='1' then
            light <= "000110";
-- end if;
when sr3 =>
-- if tick='1' then
            light <= "000111";
-- end if;
      end case;
   end process;
end arch;

   

Then obviously compile the design and perform simulation to verify its operation. I used EP2C20F484C8 Cyclone ii FPGA Starter board for implementation of Thunderbird Turn Signal FSM digital circuit design.

Implementation and testing:

You will use the 50MHz oscillator for clock and 4 switches for the reset signal and three control signals. You could use any FPGA board but I have compiled and tested the code on Altera provided FPGA board. I have posted below the pin assignments I used for my EP2C20F484C8 Cyclone ii FPGA Starter board:

From	To	Assignment Name	Value	Enabled
	reset	Location	PIN_L22	Yes
	h	Location	PIN_L21	Yes
	r	Location	PIN_M22	Yes
	l	Location	PIN_V12	Yes
	clk	Location	PIN_L1	Yes
	light[0]	Location	PIN_R20	Yes
	light[1]	Location	PIN_R19	Yes
	light[2]	Location	PIN_U19	Yes
	light[3]	Location	PIN_Y19	Yes
	light[4]	Location	PIN_T18	Yes
	light[5]	Location	PIN_V19	Yes

Read More

Rotating LED VHDL Lab Code With Intermediate-Sized Sequential Circuit Project Design and Procedures

Rotating LED is an intermediate-sized sequential circuit. Rotating LED lab will utilize seven-segment LED and clock functionality. VHDL language is used to implement this rotating LED logic on Altera DE1 FPGA device using  Altera Quartus design suite.

Project specification: In a seven-segment LED display, a square pattern can be created by enabling the a, b, f, and g segments or the c, d, e, and g segments. We want to design a circuit that circulates the square patterns in the four-digit seven-segment LED display. The circulating pattern could either be clockwise or counter-clockwise depending on the user input. The clockwise circulating pattern is shown above, just to give you an idea how we want to implement our rotating LED circuit logic. The control signals of the circuit can specify the rotation speed, the direction of rotation (i.e., clockwise or counterclockwise), and pause the operation. The rotating LED circuit design must be synchronous. We will use 4 switches for the control signals and 50MHz oscillator for clock from DE1 Altera FPGA board. The input and output signals for rotating LED logic circuit will be as follows:

Inputs:
• clk: 50 MHz clock signal from the DE1 board.
• pa: 1-bit enable signal. The circulation pauses when it is 1.
• cw: 1-bit direction signal. The pattern circulates clockwise when it is 1 and counter
clockwise when it is 0.
• sp: 2-bit speed control:
• 00: each pattern stays 20 ms
• 01: each pattern stays 40 ms
• 10: each pattern stays 80 ms
• 11: each pattern stays 160 ms

Output:
• Four seven-segment LED displays.

Design Procedures: We can divide rotating LED circuit into four segments and finally we can add up a wrapping VHDL code to instantiate all the modules. Lets first go through each module required to do the rotating LED circuit lab with the VHDL code provided:

Counter 1: generate a one-clock pulse (tick1) every 10 ms.


VHDL module Code to generate one clock pulse every 10 ms:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_1 is
   port(
      clk: in std_logic;
      tick1: out std_logic
   );
end counter_1;
architecture arch of counter_1 is
   constant DVSR: integer:=500000;
   signal ms_reg, ms_next: unsigned(18 downto 0);
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         ms_reg <= ms_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01(10ms) sec tick generator: mod-500000
   ms_next <=
      (others=>'0') when ms_reg=DVSR else
      ms_reg + 1;
   tick1 <= '1' when ms_reg=DVSR else '0';
end arch;   

Counter 2: utilizes tick1 pulse and generates a one-clock pulse (tick2) every 20 ms, 40 ms, 80 ms or 160 ms based on the sp input signal.

VHDL module Code to control the speed of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_2 is
   port(
      clk: in std_logic;
tick1: in std_logic;
sp: in std_logic_vector(1 downto 0);
      tick2: out std_logic
   );
end counter_2;
architecture arch of counter_2 is
   signal d1_reg, d0_reg: unsigned(3 downto 0);
   signal d1_next, d0_next: unsigned(3 downto 0);
   signal d1_en, d0_en: std_logic;
   signal d0_tick, tick_20ms, tick_40ms, tick_80ms, tick_160ms: std_logic;
begin
   -- register
   process(clk)
   begin
      if (clk'event and clk='1') then
         d1_reg <= d1_next;
         d0_reg <= d0_next;
      end if;
   end process;
   -- next-state logic
   -- 0.01 sec counter
   d0_en <= '1' when tick1='1' else '0';
   d0_next <=
      "0000" when (d0_en='1' and d0_reg=15) else
      d0_reg + 1 when d0_en='1' else
      d0_reg;
    tick_20ms <= '1' when d0_reg=2 else '0';
tick_40ms <= '1' when d0_reg=4 else '0';
tick_80ms <= '1' when d0_reg=8 else '0';
d0_tick <= '1' when d0_reg=9 else '0';
   -- .1 sec counter
   d1_en <= '1' when tick1='1' and d0_tick='1' else '0';
   d1_next <=
      "0000" when (d1_en='1' and d1_reg=9) else
      d1_reg + 1 when d1_en='1' else
      d1_reg;
   tick_160ms <= '1' when (d1_reg=1 and d0_reg=6) else '0';
   -- output logic
with sp select
      tick2 <=   tick_20ms when "00",
                 tick_40ms when "01",
                 tick_80ms when "10",
                 tick_160ms when others;
end arch;

Counter 3: mod-8 counter that utilizes tick2 pulse and can pause, count up and count down.

VHDL module Code for mod 8 counter to control the direction of rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity counter_3 is
   generic(
      N: integer := 3;     -- number of bits
      M: integer := 8      -- mod-M
  );
   port(
      clk: in std_logic;
      tick2, cw, pa: in std_logic;
      q: out std_logic_vector(N-1 downto 0)
   );
end counter_3;
architecture arch of counter_3 is
   signal r_regf, r_reg1, r_reg2: unsigned(N-1 downto 0);
   signal r_nextf, r_next1, r_next2: unsigned(N-1 downto 0);
begin
   -- register
   process(clk,pa)
   begin
      if (clk'event and clk='1' and tick2='1' and pa='0') then
         r_regf <= r_nextf;
         r_reg1 <= r_next1;
         r_reg2 <= r_next2;
end if;
   end process;
   -- next-state logic
r_next1 <= (others=>'0') when r_reg1=(M-1) else
             r_reg1 + 1;
r_next2 <= (others=>'1') when r_reg2=(0) else
             r_reg2 - 1;
r_nextf <= r_next1 when(cw='1') else
 r_next2;
-- output logic
   q <= std_logic_vector(r_regf);
end arch;

Decoding Circuit: A decoding circuit that generates the desired LED patterns.

VHDL module code for decoding rotating LED circuit:

library ieee;
use ieee.std_logic_1164.all;
entity decoder_rotatingLED is
port
(
input: in std_logic_vector(2 downto 0);
en: out std_logic_vector(27 downto 0)
);
end decoder_rotatingLED;
architecture arch of decoder_rotatingLED is
begin
process(input)
begin
case input  is
            when "000" =>   en <= "0011100111111111111111111111";
            when "001" =>   en <= "1111111001110011111111111111";
            when "010" =>   en <= "1111111111111100111001111111";
            when "011" =>   en <= "1111111111111111111110011100";
            when "100" =>   en <= "1111111111111111111110100011";
            when "101" =>   en <= "1111111111111101000111111111";
            when "110" =>   en <= "1111111010001111111111111111";
            when "111" =>   en <= "0100011111111111111111111111";
end case;
end process;
end arch;

Final Wrapping up circuit for rotating LED circuit which will instantiate all the modules defined above(counter1, counter2, counter3, decoding circuit). In Altera Quartus design suite, this final rotatingLED VHDL module will be set as top level entity declaration before compiling.

VHDL module Code for rotatingLED is:

library ieee;
use ieee.std_logic_1164.all;
entity rotatingLED is
port
(
final_clk: in std_logic;
final_pa, final_cw: in std_logic;
final_sp: in std_logic_vector(1 downto 0);
hex3, hex2, hex1, hex0: out std_logic_vector(6 downto 0)
);
end rotatingLED;
architecture arch of rotatingLED is
signal temp0, temp1: std_logic;
signal temp2: std_logic_vector(2 downto 0);
signal cycle: std_logic_vector(27 downto 0);
begin
c1_unit: entity work.counter_1(arch)
port map(clk=>final_clk, tick1=>temp0);
c2_unit: entity work.counter_2(arch)
port map(clk=>final_clk, tick1=>temp0, sp=>final_sp, tick2=>temp1);
c3_unit: entity work.counter_3(arch)
port map(clk=>final_clk, tick2=>temp1, pa=>final_pa, cw=>final_cw, q=>temp2);
decoder_rotatingLED_unit: entity work.decoder_rotatingLED(arch)
port map(input=>temp2, en=>cycle);
hex3 <= cycle(27 downto 21);
hex2 <= cycle(20 downto 14);
hex1 <= cycle(13 downto 7);
hex0 <= cycle(6 downto 0);
end arch;

We will also do the pin assignment for this rotating LED circuit lab as follows:

From	To	Assignment Name	Value	Enabled
	final_pa	Location	PIN_L22	Yes
	final_cw	Location	PIN_L21	Yes
	final_sp[0]	Location	PIN_M22	Yes
	final_sp[1]	Location	PIN_V12	Yes
	final_clk	Location	PIN_L1	Yes
	hex0[0]	Location	PIN_J2	Yes
	hex0[1]	Location	PIN_J1	Yes
	hex0[2]	Location	PIN_H2	Yes
	hex0[3]	Location	PIN_H1	Yes
	hex0[4]	Location	PIN_F2	Yes
	hex0[5]	Location	PIN_F1	Yes
	hex0[6]	Location	PIN_E2	Yes
	hex1[0]	Location	PIN_E1	Yes
	hex1[1]	Location	PIN_H6	Yes
	hex1[2]	Location	PIN_H5	Yes
	hex1[3]	Location	PIN_H4	Yes
	hex1[4]	Location	PIN_G3	Yes
	hex1[5]	Location	PIN_D2	Yes
	hex1[6]	Location	PIN_D1	Yes
	hex2[0]	Location	PIN_G5	Yes
	hex2[1]	Location	PIN_G6	Yes
	hex2[2]	Location	PIN_C2	Yes
	hex2[3]	Location	PIN_C1	Yes
	hex2[4]	Location	PIN_E3	Yes
	hex2[5]	Location	PIN_E4	Yes
	hex2[6]	Location	PIN_D3	Yes
	hex3[0]	Location	PIN_F4	Yes
	hex3[1]	Location	PIN_D5	Yes
	hex3[2]	Location	PIN_D6	Yes
	hex3[3]	Location	PIN_J4	Yes
	hex3[4]	Location	PIN_L8	Yes
	hex3[5]	Location	PIN_F3	Yes
	hex3[6]	Location	PIN_D4	Yes

Please leave your feedback to improve the quality of the code on this site. Check out our selection VHDL related posts and lab codes.

Read More

BCD Incrementor Lab VHDL Code (binary-coded-decimal and show digits on 7-segment LED's)

Project specification:
The binary-coded-decimal (BCD) format uses 4 bits to represent 10 decimal digits. For example, 259 is represented as "0010 0101 1001" in BCD format. A BCD incrementor adds 1 to a number in BCD format. For example, after incrementing, "0010 0101 1001" (i.e., 259) becomes "0010 0110 0000" (i.e., 260). We want to design the circuit and display the results on three 7- segment LED displays.

The input and output of the incrementor are
input:
b2, b1, b0: three 4-bit inputs representing 3 BCD digits and b2 is the most
significant digit.
output:
y2, y1, y0: three 4-bit outputs representing 3 incremented BCD digits and y2 is
the most significant digit.

BASIC INCREMENTOR VHDL CODE:

library ieee;
use ieee.std_logic_1164.all;
entity incrementor is
port
(
x: in std_logic_vector(3 downto 0);
y: out std_logic_vector(3 downto 0);
E: out std_logic
);
end incrementor;
architecture inc_arch of incrementor is
signal p: std_logic_vector(11 downto 0);
begin
--evaluate intermediate signals
p(11) <= (not x(3)) and x(2) and x(1) and x(0);
p(10) <= x(3) and (not x(2)) and (not x(1)) and (not x(0));
p(9) <= (not x(3)) and x(2) and (not x(0));
p(8) <= (not x(3)) and x(2) and (not x(1));
p(7) <= (not x(3)) and (not x(2)) and x(1) and x(0);
p(6) <= (not x(3)) and (not x(1)) and x(0);
p(5) <= (not x(3)) and (not x(0)) and x(1);
p(4) <= (not x(2)) and (not x(1)) and (not x(0));
p(3) <= (not x(3)) and (not x(0));
p(2) <= x(3) and x(2);
p(1) <= x(3) and x(0);
p(0) <= x(3) and x(1);
--get the final outputs using intermediate signal values
y(3) <= p(11) or p(10);
y(2) <= p(9) or p(8) or p(7);
y(1) <= p(6) or p(5);
y(0) <= p(4) or p(3);
E <= p(2) or p(1) or p(0);
end inc_arch; 

MUX VHDL CODE USED TO SELECT OUTPUT FROM INCREMENTOR:

--***************************************************************
--
-- Author: Sikander
--
-- File: mux_for_invertion.vhd
-- Design units:
-- ENTITY mux_for_invertion
-- ARCHITECTURE invertion
-- Purpose: to select particular input
-- Inputs: 2 4-bit inputs and ctl
-- Outputs: 1 4-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(
a,b: in std_logic_vector(3 downto 0);
ctl: in std_logic;
output: out std_logic_vector(3 downto 0)
);
end mux;
architecture selection of mux is
signal p,q: std_logic_vector(3 downto 0);
begin
p <= (not ctl) & (not ctl) & (not ctl) & (not ctl);
q <= ctl & ctl & ctl & ctl;
output <= (a and p) or (b and q);
end selection;

DISPLAY DIGITS ON 7-SEGMENT LED OF FPGA DEVICE VHDL CODE:

--***************************************************************
--
-- Author: Sikander
--
-- File: hex_toshow_LES.vhd
-- Design units:
-- ENTITY hex_toshow_LES
-- ARCHITECTURE arch
-- Purpose: to use LED
-- Inputs: 4-bit input
-- Outputs: 7-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity hex_toshow_LES is
port(
bin: in std_logic_vector(3 downto 0);
sseg: out std_logic_vector(6 downto 0)
);
end hex_toshow_LES;
architecture arch of hex_toshow_LES is
begin
with bin select
sseg <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;

end arch;

FINAL BCD INCREMENTOR VHDL CODE:

--***************************************************************
--
-- Author: Sikander
--
-- File: bcd_inc.vhd
-- Design units:
-- ENTITY bcd_inc
-- ARCHITECTURE bcd_arch
-- Purpose: to function as 3 digit BCD incrementor
-- Inputs: 3 4-bit input
-- Outputs: 3 4-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity bcd_inc is
port
(
b2, b1, b0: in std_logic_vector(3 downto 0);
y2, y1, y0: out std_logic_vector(3 downto 0)
);
end bcd_inc;
architecture bcd_arch of bcd_inc is
signal p,q,r,s: std_logic_vector(3 downto 0);
signal F,G: std_logic;
begin
b0_unit: entity work.incrementor(inc_arch)
port map(x=>b0, y=>y0, E=>F);
b1_unit: entity work.incrementor(inc_arch)
port map(x=>b1, y=>p, E=>G);
b2_unit: entity work.incrementor(inc_arch)
port map(x=>b2, y=>q);
mux1_unit: entity work.mux(selection)
port map(a=>b1, b=>p, ctl=>F, output=>y1);
mux2_unit: entity work.mux(selection)
port map(a=>b2, b=>q, ctl=>G, output=>y2);
end bcd_arch; 

Read More

FPGA: A field-programmable gate array, a type of Logic Chip that can be Programmed

In simple words, a field-programmable gate array (FPGA) is a a type of logic chip that can be programmed.
FPGA is an integrated circuit designed to be configured by the customer or designer after manufacturing—that is why called "field-programmable". An FPGA is similar to a PLD, but whereas PLDs are generally limited to hundreds of gates, FPGAs support thousands of gates. Once the design is set, hardwired chips are produced for faster performance. They are especially popular for prototyping integrated circuit designs.
The FPGA configuration is generally specified using a hardware description language (HDL), similar to that used for an application-specific integrated circuit (ASIC) (circuit diagrams were previously used to specify the configuration, as they were for ASICs, but this is increasingly rare).

FPGAs can be used to implement any logical function that an ASIC could perform. The ability to update the functionality after shipping, partial re-configuration of the portion of the design and the low non-recurring engineering costs relative to an ASIC design (notwithstanding the generally higher unit cost), offer advantages for many applications.
FPGAs contain programmable logic components called "logic blocks", and a hierarchy of reconfigurable interconnects that allow the blocks to be "wired together"—somewhat like many (changeable) logic gates that can be inter-wired in (many) different configurations. Logic blocks can be configured to perform complex combinational functions, or merely simple logic gates like AND and XOR. In most FPGAs, the logic blocks also include memory elements, which may be simple flip-flops or more complete blocks of memory.

Xilinx Co-Founders, Ross Freeman and Bernard Vonderschmitt, invented the first commercially viable field programmable gate array in 1985 – the XC2064. The XC2064 had programmable gates and programmable interconnects between gates, the beginnings of a new technology and market. The XC2064 boasted a mere 64 configurable logic blocks (CLBs), with two 3-input lookup tables (LUTs). More than 20 years later, Freeman was entered into the National Inventors Hall of Fame for his invention.

FPGA Market:
Xilinx is the top leader in providing high quality FPGA with 51% market, Altera is the top competitor of Xilinx With 34% market.

Read More

Dual Priority Encoder VHDL code (A dual-priority encoder returns the codes of the highest and second-highest priority requests)

Project specification:
A dual-priority encoder returns the codes of the highest and second-highest priority requests.
The input is the 10-bit r signal, in which the r(10) has the highest priority and r(1) has the lowest
priority. The outputs are fst and snd, which are the 4-bit binary codes of the highest and secondhighest
priority requests, respectively. The input and output signals are
   input:
r: 10-bit input request

   output:
fst: 4-bit output, the binary code of the highest priority request
snd: 4-bit output, the binary code of the second-highest priority request


Design Procedures:
   1. Encoder circuit
The best way to derive efficient VHDL code is to think in terms of hardware. First, draw a
conceptual top-level schematic diagram (i.e., what you will do if no HDL/synthesis software is
available) and then derive the code accordingly.


   2. Testing circuit with 7-segment display
Use 10-bit switch as the request signal. Decode the fst and snd signals and display the two
codes in hex format in two seven-segment LED displays.


   3. Implementation with truth table
A combination circuit can be exhaustively specified by a truth table, which can be realized by
one VHDL selected assignment statement. For the 10-request dual-priority encoder in this
experiment, a 210-by-8 table is needed. The architecture body looks like
architecture table_arch of dual_prio is
signal both: std_logic_vector(7 downto 0); -- codes of 1st & 2nd
begin
with r select
both <=
"00000000" when "0000000000", -- 1st:0; 2nd:0
"00010000" when "0000000001", -- 1st:1; 2nd:0
"00100000" when "0000000010", -- 1st:2; 2nd:0
"00100001" when "0000000011", -- 1st:2; 2nd:1
... -- 1024 lines
fst <= both(7 downto 4);
snd <= both(3 downto 0);
end table_arch;
While the code is straightforward, manually completing the 1024 rows is tedious and time
consuming. If you wish, you can write a program in the language of your choice (C, Java, Perl,
etc.) to generate theses rows and copy/paste them to the VHDL code.

Priority encode VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity prio_encoder is
port
(
p: in std_logic_vector(10 downto 1);
pcode: out std_logic_vector(3 downto 0)
);
end prio_encoder;
architecture encode of prio_encoder is
begin
process(p)
begin
if (p(10)='1') then
pcode <= "1010";
elsif (p(9)='1')then
pcode <= "1001";
elsif (p(8)='1')then
pcode <= "1000";
elsif (p(7)='1')then
pcode <= "0111";
elsif (p(6)='1')then
pcode <= "0110";
elsif (p(5)='1')then
pcode <= "0101";
elsif (p(4)='1')then
pcode <= "0100";
elsif (p(3)='1')then
pcode <= "0011";
elsif (p(2)='1')then
pcode <= "0010";
elsif (p(1)='1')then
pcode <= "0001";
else
pcode <= "0000";
end if;
end process;
end encode;

4 to 10 bit Decoder VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity decoder_4_10 is
   port(
      x: in std_logic_vector(3 downto 0);
      y: out std_logic_vector(10 downto 1)
   );
end decoder_4_10;
architecture if_arch of decoder_4_10 is begin
   process(x)
   begin
      if (x="1010") then
         y <= "1000000000";
      elsif (x="1001")then
         y <= "0100000000";
      elsif (x="1000")then
         y <= "0010000000";
      elsif (x="0111")then
         y <= "0001000000";
      elsif (x="0110")then
         y <= "0000100000";
      elsif (x="0101")then
         y <= "0000010000";
      elsif (x="0100")then
         y <= "0000001000";
      elsif (x="0011")then
         y <= "0000000100";
      elsif (x="0010")then
         y <= "0000000010";
      elsif (x="0001")then
         y <= "0000000001";
      else
y <= "0000000000";
      end if;
   end process;
end if_arch;

Dual priority bit checker VHDL code:

use ieee.std_logic_1164.all;
entity dual_prio is
 port
 (
r: in std_logic_vector(9 downto 0);
fst, snd: out std_logic_vector(3 downto 0);
hex0, hex1: out std_logic_vector(6 downto 0)
 );
end dual_prio;
architecture func_dual_prio of dual_prio is
--signal p: std_logic_vector(10 downto 1);
signal q: std_logic_vector(3 downto 0);
signal s: std_logic_vector(3 downto 0);
--signal m: std_logic_vector(3 downto 0);
signal n: std_logic_vector(10 downto 1);
signal z: std_logic_vector(10 downto 1);
begin
prio1_unit: entity work.prio_encoder(encode)
      port map(p=>r, pcode=>q);
fst <= q;
hex1_unit: entity work.hex_toshow_LES(arch)
      port map(bin=>q, sseg=>hex1);
deco1_unit: entity work.decoder_4_10(if_arch)
      port map(x=>q, y=>n);
z <= (not n) and r;
prio2_unit: entity work.prio_encoder(encode)
      port map(p=>z, pcode=>s);
snd <= s;
hex0_unit: entity work.hex_toshow_LES(arch)
      port map(bin=>s, sseg=>hex0);
end func_dual_prio;

LED hexes to show LES VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity hex_toshow_LES is
   port(
      bin: in std_logic_vector(3 downto 0);
      sseg: out std_logic_vector(6 downto 0)
   );
end hex_toshow_LES;
architecture arch of hex_toshow_LES is
begin
with bin select
         sseg <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;
end arch; 

Read More

Comparator Circuit (2-bit, 4-bit, 8-bit) VHDL code (A comparator compares two n-bit inputs and generates three status signals)

Project specification:
A comparator compares two n-bit inputs and generates three status signals. The input and
output signals are
   input:

a: n-bit input operand
b: n-bit input operand
  output:

lt: 1-bit output. It is asserted when a is larger than b.
st: 1-bit output. It is asserted when a is smaller than b.
eq: 1-bit output. It is asserted when a is equal to than b.


Design Procedures:

   1. 2-bit comparator
In a 2-bit comparator, the input size of an operand (i.e., n) is 2. The circuit should have four inputs and three outputs.

   2.4-bit comparator

In a 4-bit comparator, the input size of an operand (i.e., n) is 4. The circuit should have eight inputs and three outputs. The circuit can be constructed from two 2-bit comparators of theprevious section.

   3. 4-bit comparator with 7-segment display
An additional seven-segment LED display can be used to show the output status. The display will show “L”, “E” or “S” pattern for the larger-than, equal-to, or smaller-than condition. Conditional signal assignment or selected signal assignment statements can be used for the 7- sgement LED circuit.

   4. 8-bit comparator
In an 8-bit comparator, the input size of an operand (i.e., n) is 8. The circuit should have 16 inputs and three outputs. The circuit can be constructed from the previously designed comparators.

2-bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp2 is
port(
a,b: in std_logic_vector(1 downto 0);
lt, st, eq: out std_logic
);
end comp2;
architecture bit2_Comparator of comp2 is
signal p0,p1,p2,p3,p4,p5,p6,p7,p8,p9: std_logic;
begin
eq <= p0 or p1 or p2 or p3;
p0 <= ( (not a(1)) and (not a(0)) and (not b(1)) and (not b(0)) );
p1 <= ( (not a(1)) and a(0) and (not b(1)) and b(0) );
p2 <= ( a(1) and (not a(0)) and b(1) and (not b(0)) );
p3 <= ( a(1) and a(0) and b(1) and b(0) );
st <= p4 or p5 or p6;
p4 <= ( (not a(0)) and b(1) and b(0) );
p5 <= ( (not a(1)) and (not a(0)) and b(0) );
p6 <= ( (not a(1)) and b(1) );
lt <= p7 or p8 or p9;
p7 <= ( a(1) and a(0) and (not b(0)) );
p8 <= ( a(1) and (not b(1)) );
p9 <= ( a(0) and (not b(1)) and (not b(0)) );
end bit2_Comparator;

4-Bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(
a,b: in std_logic_vector(3 downto 0);
lt, st, eq: out std_logic;
LED: out std_logic_vector(6 downto 0)
);
end comp4;
architecture bit4_Comparator of comp4 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(3), a(0)=>a(2), b(1)=>b(3), b(0)=>b(2), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(1), a(0)=>a(0), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
end bit4_Comparator;

4-bit comparator with 7-segment display:

library ieee;
use ieee.std_logic_1164.all;
entity comp4 is
port(
a,b: in std_logic_vector(3 downto 0);
lt, st, eq: out std_logic;
LED: out std_logic_vector(6 downto 0)
);
end comp4;
architecture bit4_Comparator of comp4 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(3), a(0)=>a(2), b(1)=>b(3), b(0)=>b(2), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp2(bit2_Comparator)
port map(a(1)=>a(1), a(0)=>a(0), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
LED(6) <= l1 or (e1 and l0);
LED(4) <= s1 or (e1 and s0);
LED(2) <= l1 or (e1 and l0) or (e1 and e0);
LED(1) <= e1 or l1 or s1;
LED(0) <= l1 or (e1 and l0);

   sseg_unit: entity work.hex_toshow_LES(arch)
port map(s=>st, l=>lt, sseg=>LED);
"0001000" when (l='1') else  --larger
"0010010" when (s='1') else --smaller
"0000110";
end bit4_Comparator;

8-bit Comparator VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity comp8 is
port(
a,b: in std_logic_vector(7 downto 0);
lt, st, eq: out std_logic
);
end comp8;
architecture bit8_Comparator of comp8 is
signal e1,e0,s1,s0,l1,l0: std_logic;
begin
comp1_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(7), a(2)=>a(6), a(1)=>a(5), a(0)=>a(4), b(3)=>b(7), b(2)=>b(6), b(1)=>b(5), b(0)=>b(4), eq=>e1, st=>s1, lt=>l1 );
comp2_unit: entity work.comp4(bit4_Comparator)
port map(a(3)=>a(3), a(2)=>a(2), a(1)=>a(1), a(0)=>a(0), b(3)=>b(3), b(2)=>b(2), b(1)=>b(1), b(0)=>b(0), eq=>e0, st=>s0, lt=>l0 );
eq <= e1 and e0;
lt <= l1 or (e1 and l0);
st <= s1 or (e1 and s0);
end bit8_Comparator;

Read More

Majority Circuit VHDL Code (a circuit that counts 4 votes and displays the results)

Project specification:
We want to design a circuit that counts 4 votes and displays the results. Only VHDL logical operators (i.e., and, or, not, and xor) can be used in VHDL code and no process is allowed.

Our input and outputs should be as follows:

1. v: 4-bit inputs representing 4 votes, with 1 for yes and 0 for no..output
2. fail: 1-bit output. It is asserted when the motion fails (i.e., less than two 1’s).
3. tie: 1-bit output. It is asserted when the vote is a tie (i.e., two 1’s and two 0’s).
4. pass: 1-bit output. It is asserted when there is a majority (i.e., three or four 1’s).

Majority Circuit VHDL code:

library ieee;
use ieee.std_logic_1164.all;
entity majority_circuit is
port(
v: in std_logic_vector(3 downto 0);
fail, tie, pass: out std_logic
);
end majority_circuit;
architecture decisionMaker of majority_circuit is
signal p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13: std_logic;
begin
fail <= p0 or p1 or p2 or p3;
p0 <= ((not v(3)) and (not v(2)) and (not v(0)));
p1 <= ((not v(3)) and (not v(2)) and (not v(1)));
p2 <= ((not v(3)) and (not v(1)) and (not v(0)));
p3 <= ((not v(2)) and (not v(1)) and (not v(0)));
tie <= p4 or p5 or p6 or p7 or p8 or p9;
p4 <= ((not v(3)) and (not v(2)) and v(1) and v(0));
p5 <= ((not v(3)) and v(2) and (not v(1)) and v(0));
p6 <= ((not v(3)) and v(2) and v(1) and (not v(0)));
p7 <= (v(3) and (not v(2)) and (not v(1)) and v(0));
p8 <= (v(3) and (not v(2)) and v(1) and (not v(0)));
p9 <= (v(3) and v(2) and (not v(1)) and (not v(0)));
pass <= p10 or p11 or p12 or p13;
p10 <= (v(3) and v(2) and v(0));
p11 <= (v(2) and v(1) and v(0));
p12 <= (v(3) and v(1) and v(0));
p13 <= (v(3) and v(2) and v(1));
end decisionMaker;

Read More

4-Request Priority Encoder VHDL Code (Conditional Signal Assignment)

Conditional Signal Assignment
Syntax:
• Overall effect somewhat like if-then-else
• Simplified syntax:
signal_name
<= value_expr_1 when boolean_expr_1 else value_expr_2 when boolean_expr_2 else value_expr_3 when boolean_expr_3 else . . . value_expr_n Sample VHDL code for 4-request priority encoder:
library ieee;
use ieee.std_logic_1164.all;
entity prio_encoder is
port(
r: in std_logic_vector(4 downto 1);
pcode: out std_logic_vector(2 downto 0)
);
end prio_encoder;

architecture cond_arch of prio_encoder is
begin
pcode <= "100" when (r(4)='1') else
"011" when (r(3)='1') else
"010" when (r(2)='1') else
"001" when (r(1)='1') else
"000";
end cond_arch;

Read More

2 to 4 Decoder VHDL Code (Case conditional Statements)

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.
e.g. n-to-2n, binary-coded decimal decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output".

library ieee;

use ieee.std_logic_1164.all;

entity decoder_2_4 is

port(

a: in std_logic_vector(1 downto 0);

en: in std_logic;

y: out std_logic_vector(3 downto 0)

);

end decoder_2_4;

architecture case_arch of decoder_2_4 is

signal s: std_logic_vector(2 downto 0);

begin

s <= en & a;

process(s)

begin

case s is

when "000"|"001"|"010"|"011" =>

y <= "0001";

when "100" =>

y <= "0001";

when "101" =>

y <= "0010";

when "110" =>

y <= "0100";

when others =>

y <= "1000";

end case;

end process;

end case_arch;

Read More

WORKING 32-BIT ALU VHDL CODE: To Implement ALU and control circuit for 32bit MIPS CPU computer architecture

Project Description: Implement 32-bit ALU, ALU control and main control circuit that supports add, sub, slt, and, or, nor, lw, sw, beq, bne, j instructions using HDL.

This project contains 15 files as follows:

4 files for 32-bit ALU, 1 file for ALUctrl, 1 file for main control circuit, 3 simulation test case files for 32-bit ALU, 3 simulation test case files for ALUctrl and 3 simulation test case files for main control circuit.

Brief info about what is this ALU thing:

In computing, an arithmetic logic unit (ALU) is a digital circuit that performs arithmetic and logical operations. The ALU is a fundamental building block of the central processing unit of a computer, and even the simplest microprocessors contain one for purposes such as maintaining timers. The processors found inside modern CPUs and graphics processing units (GPUs) accommodate very powerful and very complex ALUs; a single component may contain a number of ALUs.

Now lets get started >

32-bit ALU:

(1)   mux_for_invertion file inverts the input signal(a or b) to execute sub, slt, nor, beq and bne instructions. Its 2-to-1 mux basically.

(2)   mux_for_operation file deals with selecting what kind of operation is needed to be executed using 4-to-1 mux. It would select from and(00), or(01), add/sub(10) and slt(11).

(3)   alu_1bit file perform all the required instructions but only 1 bit.

(4)   alu file perform functions of 32-bit ALU in 32 bit mips processor.

ALUctrl: It extracts 4-bit alu control signal from mips instruction.

Main control: Main control circuit uses information from 6-bit op code to control 11 output control signals.

Simulation files for Model Sim software: Simulation was done on ModelSim - Altera, which is free simulating software from Altera which can smoothly simulate your vhdl code files. ModelSim - Altera also provides pretty nice ways to debug your vhdl code, it allows you to literally go through every single line of execution code while your program is running(how registers are updating new values, how control signals are getting new values, either alucontrol or main control). There are 3 individual simulation test case files, 1 for each, to check the functionality of 32-bit ALU, ALUctrl and main control signal files.

   

**********************************************************************************
START OF 1BIT ALU VHDL FILE
**********************************************************************************


--*************************************************************** 
--  
-- Author: Sikander
--    
-- File: alu_1bit.vhd 
-- Design units: 
--  ENTITY alu_1bit  
--  ARCHITECTURE alu_1bit_operation
-- Purpose: perform functions of 1-bit ALU   
--  Inputs:  1 bit input a, b, carryIn, less, set_slt and 4 bit ALUctl control signal
--  Outputs: 1 bit result, carryOut
--   
-- Library/Package: 
--  ieee.std_logic_1164: to use std_logic 
-- 
-- Software/Version:  
--  Simulated by: Altera Quartus v11.0 
--  Synthesized by: Altera Quartus v11.0 
--   
-- Revision History 
--  Version 1.0: 
--  Date: 9/29/2006 
--  Comments: Original  
-- 
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity alu_1bit is
port(
ctrSignal: in std_logic_vector(3 downto 0);
a,b: in std_logic;
result: out std_logic;
carryOut: out std_logic;
carryIn: in std_logic;
set_slt: out std_logic;
less: in std_logic
);
end alu_1bit;
architecture alu_1bit_operation of alu_1bit is
signal a_final,b_final,and_final,or_final,add_final,slt_final,temp_result: std_logic;
begin
ainvert_unit: entity work.mux_for_invertion(invertion)
port map(input=>a, invert=>ctrSignal(3), output=>a_final);    --inverting a if needed
binvert_unit: entity work.mux_for_invertion(invertion)
port map(input=>b, invert=>ctrSignal(2), output=>b_final);    --inverting b if needed
and_final <= a_final and b_final;                                --doing and operation 
or_final <= a_final or b_final;
--carryIn <= ctrSignal(2);
add_final <= a_final xor b_final xor carryIn;
set_slt <= add_final;
carryOut <= (a_final and b_final) or (a_final and carryIn) or (b_final and carryIn);
--slt_final <= '0';
operation_unit: entity work.mux_for_operation(mux_4to1)             --passing out 4 results thru 4to1 mux
port map(control(1)=>ctrSignal(1), control(0)=>ctrSignal(0), 
input(3)=>and_final, input(2)=>or_final, input(1)=>add_final, input(0)=>less, output=>temp_result);
result <= temp_result;
end alu_1bit_operation;


**********************************************************************************
END OF 1BIT ALU VHDL FILE
**********************************************************************************


**********************************************************************************
START OF MUX OF INVERSION VHDL FILE
**********************************************************************************

--*************************************************************** 
--  
-- Author: Sikander 
--    
-- File: mux_for_invertion.vhd 
-- Design units: 
--  ENTITY mux_for_invertion  
--  ARCHITECTURE invertion
-- Purpose: to invert formal signal when needed   
--  Inputs: 1 bit input and invert
--  Outputs: 1 bit output
--   
-- Library/Package: 
--  ieee.std_logic_1164: to use std_logic 
-- 
-- Software/Version:  
--  Simulated by: Altera Quartus v11.0 
--  Synthesized by: Altera Quartus v11.0 
--   
-- Revision History 
--  Version 1.0: 
--  Date: 9/29/2006 
--  Comments: Original  
-- 
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mux_for_invertion is
port(
input: in std_logic;
invert: in std_logic;
output: out std_logic
);
end mux_for_invertion;
architecture invertion of mux_for_invertion is
begin
output <= ((not input) and invert) or (input and (not invert));
end invertion;


**********************************************************************************
END OF MUX OF INVERSION VHDL FILE
**********************************************************************************


**********************************************************************************
START OF MUX OF OPERATION VHDL FILE
**********************************************************************************

--*************************************************************** 
--  
-- Author: Sikander
--    
-- File: mux_for_operation.vhd 
-- Design units: 
--  ENTITY mux_for_operation  
--  ARCHITECTURE mux_4to1 
-- Purpose: mux to find out what instruction to execute
--  Inputs:  2 bit operation signal and 4 bit input
--  Outputs: 1 bit output
--   
-- Library/Package: 
--  ieee.std_logic_1164: to use std_logic 
-- 
-- Software/Version:  
--  Simulated by: Altera Quartus v11.0 
--  Synthesized by: Altera Quartus v11.0 
--   
-- Revision History 
--  Version 1.0: 
--  Date: 9/29/2006 
--  Comments: Original  
-- 
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mux_for_operation is
port(
control: in std_logic_vector(1 downto 0);
input: in std_logic_vector(3 downto 0);
output: out std_logic
);
end mux_for_operation;
architecture mux_4to1 of mux_for_operation is
signal temp: std_logic_vector(3 downto 0);
begin
output <= temp(3) or temp(2) or temp(1) or temp(0);
temp(3) <= (not control(1)) and (not control(0)) and input(3);
temp(2) <= (not control(1)) and control(0) and input(2);
temp(1) <= control(1) and (not control(0)) and input(1);
temp(0) <= control(1) and control(0) and input(0);
end mux_4to1;



**********************************************************************************
END OF MUX OF OPERATION VHDL FILE
**********************************************************************************


**********************************************************************************
START OF ALU CONTROL VHDL FILE
**********************************************************************************

--*************************************************************** 
--  
-- Author: Sikander
--    
-- File: aluctrl.vhd 
-- Design units: 
--  ENTITY aluctrl  
--  ARCHITECTURE aluctrl_behav 
-- Purpose: to find out alu control signal from mips instruction   
--  Inputs:  2 bit ALUOp and 6 bit Func code
--  Outputs: 4 bit ALUctl 
--   
-- Library/Package: 
--  ieee.std_logic_1164: to use std_logic 
-- 
-- Software/Version:  
--  Simulated by: Altera Quartus v11.0 
--  Synthesized by: Altera Quartus v11.0 
--   
-- Revision History 
--  Version 1.0: 
--  Date: 9/29/2006 
--  Comments: Original  
-- 
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity aluctrl is
port
(
ALUOp: in std_logic_vector(1 downto 0);
Func: in std_logic_vector(5 downto 0);
ALUctl: out std_logic_vector(3 downto 0)
);
end aluctrl;
architecture aluctrl_behav of aluctrl is
signal p0,p1,p2,p3,p4,p5,p6,p7: std_logic;
begin
ALUctl(3) <= p1;
ALUctl(2) <= p0 or p1 or p2 ;
ALUctl(1) <= p3 or p4 or p7;
ALUctl(0) <= p5 or p6;

p0 <= ALUOp(1) and (not ALUOp(0)) and (not Func(2)) and Func(1) and (not Func(0));
p1 <= ALUOp(1) and (not ALUOp(0)) and (not Func(3)) and Func(2) and Func(1) and Func(0);   --for ain also
p2 <= (not ALUOp(1)) and ALUOp(0);   
p3 <= ALUOp(1) and (not ALUOp(0)) and (not Func(3)) and (not Func(2)) and (not Func(0));
p4 <= (not ALUOp(1));
p5 <= ALUOp(1) and (not ALUOp(0)) and Func(3) and (not Func(2)) and Func(1) and (not Func(0));
p6 <= ALUOp(1) and (not ALUOp(0)) and (not Func(3)) and Func(2) and (not Func(1)) and Func(0);
p7 <= ALUOp(1) and (not ALUOp(0)) and Func(3) and (not Func(2)) and (not Func(0)) and Func(1);
end aluctrl_behav;

**********************************************************************************
END OF ALU CONTROL VHDL FILE
**********************************************************************************


**********************************************************************************
START OF 32-BIT ALU VHDL FILE
**********************************************************************************

--*************************************************************** 
--  
-- Author: Sikander
--    
-- File: alu.vhd 
-- Design units: 
--  ENTITY alu  
--  ARCHITECTURE alu_behav 
-- Purpose: perform functions of 32-bit ALU in 32 bit mips processor   
--  Inputs:  32 bit a,b and 4 bit ALUctl control signal
--  Outputs: 32 bit ALUOut and 1 bit zero flag
--   
-- Library/Package: 
--  ieee.std_logic_1164: to use std_logic 
-- 
-- Software/Version:  
--  Simulated by: Altera Quartus v11.0 
--  Synthesized by: Altera Quartus v11.0 
--   
-- Revision History 
--  Version 1.0: 
--  Date: 9/29/2006 
--  Comments: Original  
-- 
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity alu is
port
(
ALUctl: in std_logic_vector(3 downto 0);
A, B: in std_logic_vector(31 downto 0);
ALUOut: out std_logic_vector(31 downto 0);
Zero: out std_logic
);
end alu;


architecture alu_behav of alu is
signal carry: std_logic_vector(31 downto 0);
signal get,set: std_logic;
signal aout: std_logic_vector(31 downto 0);
begin
   bit0_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(0), b=>B(0), ctrSignal=>ALUctl, carryIn=>ALUctl(2), less=>set, carryOut=>carry(0), result=>aout(0));
bit1_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(1), b=>B(1), ctrSignal=>ALUctl, carryIn=>carry(0), less=>'0', carryOut=>carry(1), result=>aout(1));
bit2_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(2), b=>B(2), ctrSignal=>ALUctl, carryIn=>carry(1), less=>'0', carryOut=>carry(2), result=>aout(2));
bit3_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(3), b=>B(3), ctrSignal=>ALUctl, carryIn=>carry(2), less=>'0', carryOut=>carry(3), result=>aout(3));
bit4_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(4), b=>B(4), ctrSignal=>ALUctl, carryIn=>carry(3), less=>'0', carryOut=>carry(4), result=>aout(4));
bit5_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(5), b=>B(5), ctrSignal=>ALUctl, carryIn=>carry(4), less=>'0', carryOut=>carry(5), result=>aout(5));
bit6_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(6), b=>B(6), ctrSignal=>ALUctl, carryIn=>carry(5), less=>'0', carryOut=>carry(6), result=>aout(6));
bit7_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(7), b=>B(7), ctrSignal=>ALUctl, carryIn=>carry(6), less=>'0', carryOut=>carry(7), result=>aout(7));
bit8_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(8), b=>B(8), ctrSignal=>ALUctl, carryIn=>carry(7), less=>'0', carryOut=>carry(8), result=>aout(8));
bit9_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(9), b=>B(9), ctrSignal=>ALUctl, carryIn=>carry(8), less=>'0', carryOut=>carry(9), result=>aout(9));
bit10_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(10), b=>B(10), ctrSignal=>ALUctl, carryIn=>carry(9), less=>'0', carryOut=>carry(10), result=>aout(10));
bit11_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(11), b=>B(11), ctrSignal=>ALUctl, carryIn=>carry(10), less=>'0', carryOut=>carry(11), result=>aout(11));
bit12_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(12), b=>B(12), ctrSignal=>ALUctl, carryIn=>carry(11), less=>'0', carryOut=>carry(12), result=>aout(12));
bit13_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(13), b=>B(13), ctrSignal=>ALUctl, carryIn=>carry(12), less=>'0', carryOut=>carry(13), result=>aout(13));
bit14_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(14), b=>B(14), ctrSignal=>ALUctl, carryIn=>carry(13), less=>'0', carryOut=>carry(14), result=>aout(14));
bit15_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(15), b=>B(15), ctrSignal=>ALUctl, carryIn=>carry(14), less=>'0', carryOut=>carry(15), result=>aout(15));
bit16_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(16), b=>B(16), ctrSignal=>ALUctl, carryIn=>carry(15), less=>'0', carryOut=>carry(16), result=>aout(16));
bit17_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(17), b=>B(17), ctrSignal=>ALUctl, carryIn=>carry(16), less=>'0', carryOut=>carry(17), result=>aout(17));
bit18_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(18), b=>B(18), ctrSignal=>ALUctl, carryIn=>carry(17), less=>'0', carryOut=>carry(18), result=>aout(18));
bit19_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(19), b=>B(19), ctrSignal=>ALUctl, carryIn=>carry(18), less=>'0', carryOut=>carry(19), result=>aout(19));
bit20_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(20), b=>B(20), ctrSignal=>ALUctl, carryIn=>carry(19), less=>'0', carryOut=>carry(20), result=>aout(20));
bit21_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(21), b=>B(21), ctrSignal=>ALUctl, carryIn=>carry(20), less=>'0', carryOut=>carry(21), result=>aout(21));
bit22_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(22), b=>B(22), ctrSignal=>ALUctl, carryIn=>carry(21), less=>'0', carryOut=>carry(22), result=>aout(22));
bit23_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(23), b=>B(23), ctrSignal=>ALUctl, carryIn=>carry(22), less=>'0', carryOut=>carry(23), result=>aout(23));
bit24_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(24), b=>B(24), ctrSignal=>ALUctl, carryIn=>carry(23), less=>'0', carryOut=>carry(24), result=>aout(24));
bit25_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(25), b=>B(25), ctrSignal=>ALUctl, carryIn=>carry(24), less=>'0', carryOut=>carry(25), result=>aout(25));
bit26_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(26), b=>B(26), ctrSignal=>ALUctl, carryIn=>carry(25), less=>'0', carryOut=>carry(26), result=>aout(26));
bit27_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(27), b=>B(27), ctrSignal=>ALUctl, carryIn=>carry(26), less=>'0', carryOut=>carry(27), result=>aout(27));
bit28_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(28), b=>B(28), ctrSignal=>ALUctl, carryIn=>carry(27), less=>'0', carryOut=>carry(28), result=>aout(28));
bit29_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(29), b=>B(29), ctrSignal=>ALUctl, carryIn=>carry(28), less=>'0', carryOut=>carry(29), result=>aout(29));
bit30_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(30), b=>B(30), ctrSignal=>ALUctl, carryIn=>carry(29), less=>'0', carryOut=>carry(30), result=>aout(30));
bit31_unit: entity work.alu_1bit(alu_1bit_operation)
port map(a=>A(31), b=>B(31), ctrSignal=>ALUctl, carryIn=>carry(30), less=>'0', carryOut=>carry(31), set_slt=>get, result=>aout(31));
set <= get;
ALUOut <= aout;
Zero <= (not (aout(0) or aout(1) or aout(2) or aout(3) or aout(4) or aout(5) or aout(6) or aout(7) or 
aout(8) or aout(9) or aout(10) or aout (11) or aout (12) or aout (13) or aout (14) or aout(15) or 
aout(16) or aout(17) or aout(18) or aout(19) or aout(20) or aout(21) or aout(22) or aout(23) or 
aout(24) or aout(25) or aout(26) or aout (27) or aout (28) or aout (29) or aout (30) or aout (31)));

end alu_behav;

**********************************************************************************
END OF 32-BIT ALU VHDL FILE
**********************************************************************************


**********************************************************************************
START OF MAIN CONTROL VHDL FILE
**********************************************************************************

--***************************************************************
--
-- Author: S

ikander

--  
-- File: control.vhd
-- Design units:
--  ENTITY control
--  ARCHITECTURE control_behav
-- Purpose: function as main control circuit  
--  Inputs:  6 bit op code
--  Outputs: 11 1-bit control signals
--
-- Library/Package:
--  ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
--  Simulated by: Altera Quartus v11.0
--  Synthesized by: Altera Quartus v11.0
--
-- Revision History
--  Version 1.0:
--  Date: 9/29/2006
--  Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity control is
port
(
ID_op: in std_logic_vector(5 downto 0);
ID_ALUOp: out std_logic_vector(1 downto 0);
ID_RegDst, ID_ALUSrc: out std_logic;
ID_Branch, ID_MemRead, ID_MemWrite: out std_logic;
ID_RegWrite, ID_MemToReg: out std_logic;
ID_BranchNE, ID_Jump: out std_logic
);
end control;
architecture control_behav of control is
signal p0,p1,p2,p3,p4,p5: std_logic;
begin
   --loading values to variables using temp signals
ID_RegDst <= p0;
ID_ALUSrc <= p1 or p2;
ID_MemToReg <= p1;
ID_RegWrite <= p0 or p1;
ID_MemRead <= p1;
ID_MemWrite <= p2;
ID_Branch <= p3;
ID_ALUOp(1) <= p0;
ID_ALUOp(0) <= p3 or p4;
ID_BranchNE <= p4;
ID_Jump <= p5;
   --assinging values to temp signals
p0 <= (not ID_op(5)) and (not ID_op(4)) and (not ID_op(3)) and (not ID_op(2)) and (not ID_op(1)) and (not ID_op(0));
p1 <= ID_op(5) and (not ID_op(4)) and (not ID_op(3)) and (not ID_op(2)) and ID_op(1) and ID_op(0);
p2 <= ID_op(5) and (not ID_op(4)) and ID_op(3) and (not ID_op(2)) and ID_op(1) and ID_op(0);
p3 <= (not ID_op(5)) and (not ID_op(4)) and (not ID_op(3)) and ID_op(2) and (not ID_op(1)) and (not ID_op(0));
p4 <= (not ID_op(5)) and (not ID_op(4)) and (not ID_op(3)) and ID_op(2) and (not ID_op(1)) and ID_op(0);
p5 <= (not ID_op(5)) and (not ID_op(4)) and (not ID_op(3)) and (not ID_op(2)) and ID_op(1) and (not ID_op(0));
end control_behav;

**********************************************************************************
END OF MAIN CONTROL VHDL FILE
**********************************************************************************


**********************************************************************************
START OF 32-BIT ALU SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************

library  ieee;

use STD.TEXTIO.all;

use  ieee.std_logic_1164.all;

use ieee.numeric_std.all;

use ieee.numeric_std.all;

entity sim_alu1 is

end sim_alu1;

architecture sim_alu1_behav of sim_alu1 is

signal ALUctl : std_logic_vector(3 downto 0);

signal A,B : std_logic_vector(31 downto 0);

signal ALUOut : std_logic_vector(31 downto 0);

signal Zero : std_logic;

component alu

port(

ALUctl : in std_logic_vector(3 downto 0);

 A, B : in std_logic_vector(31 downto 0);

 ALUOut : out std_logic_vector(31 downto 0);

 Zero : out std_logic

);

end component;

begin

FA1: alu

 port map(ALUctl, A, B, ALUOut, Zero);

ALUctl <= "0111";

A <= std_logic_vector(to_unsigned(1200,32));

B <= std_logic_vector(to_unsigned(12000,32));

-- #1;

-- $display("ALUOut = ", ALUOut);

-- $display("Zero = ", Zero);

-- $finish;

PROCESS (ALUOut,Zero)

variable BufLine: line;

variable zoutput  : integer;--:std_logic_vector(31 downto 0);

variable zZero : integer;

variable tmpZero : std_logic_vector(0 downto 0);

begin

zoutput := to_integer(unsigned(ALUOut));

tmpZero(0) := Zero;

zZero := to_integer(unsigned(tmpZero));

write(bufline,string'("ALUOut: "));

write(bufline,zoutput);

writeline(output,bufline);

write(bufline, string'("Zero: "));

write(bufline,zZero);

writeline(output,bufline);

end PROCESS;

end sim_alu1_behav;

**********************************************************************************
END OF 32-BIT ALU SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************


**********************************************************************************
START OF  MAIN CONTROL SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************

library  ieee;
use STD.TEXTIO.all;
use  ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use ieee.numeric_std.all;

entity sim_control1 is

end sim_control1;

architecture sim_control1_behav of sim_control1 is


signal ID_op: std_logic_vector(5 downto 0);
signal ID_ALUOp: std_logic_vector(1 downto 0);
signal ID_RegDst, ID_ALUSrc: std_logic;
signal ID_Branch, ID_MemRead, ID_MemWrite: std_logic;
signal ID_RegWrite, ID_MemToReg: std_logic;
signal ID_BranchNE, ID_Jump: std_logic;

component control
port(
ID_op: in std_logic_vector(5 downto 0);
ID_ALUOp: out std_logic_vector(1 downto 0);
ID_RegDst, ID_ALUSrc: out std_logic;
ID_Branch, ID_MemRead, ID_MemWrite: out std_logic;
ID_RegWrite, ID_MemToReg: out std_logic;
ID_BranchNE, ID_Jump: out std_logic
);
end component;




begin
FA1: control
 port map(ID_op, ID_ALUOp, ID_RegDst, ID_ALUSrc, ID_Branch, 
ID_MemRead, ID_MemWrite, ID_RegWrite, ID_MemToReg, ID_BranchNE, ID_Jump);


ID_op <= "000000";
-- #1;
-- $display("ALUOut = ", ALUOut);
-- $display("Zero = ", Zero);
-- $finish;


PROCESS (ID_ALUOp, ID_RegDst, ID_ALUSrc, ID_Branch, 
ID_MemRead, ID_MemWrite, ID_RegWrite, ID_MemToReg, ID_BranchNE, ID_Jump)


variable BufLine: line;
variable  ALUOp: integer;
--variable ALUOp0: integer;
variable  RegDst: integer;
variable ALUSrc: integer;
variable  Branch: integer;
variable MemRead: integer;
variable  MemWrite: integer;
variable RegWrite: integer;
variable  MemToReg: integer;
variable BranchNE: integer;
variable  Jump: integer;
variable rd: std_logic_vector(0 downto 0);
variable as: std_logic_vector(0 downto 0);
variable b: std_logic_vector(0 downto 0);
variable mr: std_logic_vector(0 downto 0);
variable mw: std_logic_vector(0 downto 0);
variable rw: std_logic_vector(0 downto 0);
variable mtr: std_logic_vector(0 downto 0);
variable bne: std_logic_vector(0 downto 0);
variable j: std_logic_vector(0 downto 0);


begin
rd(0):= ID_RegDst;
as(0):= ID_ALUSrc;
b(0):= ID_Branch;
mr(0):= ID_MemRead;
mw(0):= ID_MemWrite;
rw(0):= ID_RegWrite;
mtr(0):= ID_MemToReg;
bne(0):= ID_BranchNE;
j(0):= ID_Jump;


 ALUOp:=to_integer(unsigned(ID_ALUOp));

 RegDst:=to_integer(unsigned(rd));

 ALUSrc:=to_integer(unsigned(as));
 Branch:=to_integer(unsigned(b));
 MemRead:=to_integer(unsigned(mr));
 MemWrite:=to_integer(unsigned(mw));
 RegWrite:=to_integer(unsigned(rw));
 MemToReg:=to_integer(unsigned(mtr));
 BranchNE:=to_integer(unsigned(bne));
 Jump:=to_integer(unsigned(j));
write(bufline,string'("ID_ALUOp: "));
write(bufline,ALUOp);
writeline(output,bufline);
write(bufline,string'("ID_RegDst: "));
write(bufline,RegDst);
writeline(output,bufline);
write(bufline,string'("ID_ALUSrc: "));
write(bufline,ALUSrc);
writeline(output,bufline);
write(bufline,string'("ID_Branch: "));
write(bufline,Branch);
writeline(output,bufline);
write(bufline,string'("ID_MemRead: "));
write(bufline,MemRead);
writeline(output,bufline);
write(bufline,string'("ID_MemWrite: "));
write(bufline,MemWrite);
writeline(output,bufline);
write(bufline,string'("ID_RegWrite: "));
write(bufline,RegWrite);
writeline(output,bufline);
write(bufline,string'("ID_MemToReg: "));
write(bufline,MemToReg);
writeline(output,bufline);
write(bufline,string'("ID_BranchNE: "));
write(bufline,BranchNE);
writeline(output,bufline);
write(bufline,string'("ID_Jump: "));
write(bufline,Jump);
writeline(output,bufline);


end PROCESS;
end sim_control1_behav;

**********************************************************************************
END OF MAIN CONTROL SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************


**********************************************************************************
START OF  ALU CONTROL SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************

library  ieee;
use STD.TEXTIO.all;
use  ieee.std_logic_1164.all;
use ieee.numeric_std.all;


use ieee.numeric_std.all;

entity sim_aluctrl1 is

end sim_aluctrl1;

architecture sim_aluctrl1_behav of sim_aluctrl1 is

signal ALUOp: std_logic_vector(1 downto 0);

signal Func: std_logic_vector(5 downto 0);
signal ALUctl: std_logic_vector(3 downto 0);

component aluctrl

port(
ALUOp: in std_logic_vector(1 downto 0);
Func: in std_logic_vector(5 downto 0);
ALUctl: out std_logic_vector(3 downto 0)
);
end component;




begin
FA1: aluctrl
 port map(ALUOp, Func, ALUctl);




ALUOp <= "10";
Func <= "000010";
-- #1;
-- $display("ALUOut = ", ALUOut);
-- $display("Zero = ", Zero);
-- $finish;


PROCESS (ALUctl)


variable BufLine: line;
variable tmp : integer;
begin


tmp := to_integer(unsigned(ALUctl));


write(bufline,string'("ALUctl: "));
write(bufline,tmp);
writeline(output,bufline);
end PROCESS;


end sim_aluctrl1_behav;

**********************************************************************************
END OF ALU CONTROL SIMULATION VHDL FILE FOR MODELSIM
**********************************************************************************

Read More