2 to 4 Decoder VHDL Code (Case conditional Statements)

In digital electronics, a decoder can take the form of a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different.
e.g. n-to-2n, binary-coded decimal decoders.
Enable inputs must be on for the decoder to function, otherwise its outputs assume a single "disabled" output code word. Decoding is necessary in applications such as data multiplexing, 7 segment display and memory address decoding.
The example decoder circuit would be an AND gate because the output of an AND gate is "High" (1) only when all its inputs are "High." Such output is called as "active High output". If instead of AND gate, the NAND gate is connected the output will be "Low" (0) only when all its inputs are "High". Such output is called as "active low output".

library ieee;

use ieee.std_logic_1164.all;

entity decoder_2_4 is

port(

a: in std_logic_vector(1 downto 0);

en: in std_logic;

y: out std_logic_vector(3 downto 0)

);

end decoder_2_4;

architecture case_arch of decoder_2_4 is

signal s: std_logic_vector(2 downto 0);

begin

s <= en & a;

process(s)

begin

case s is

when "000"|"001"|"010"|"011" =>

y <= "0001";

when "100" =>

y <= "0001";

when "101" =>

y <= "0010";

when "110" =>

y <= "0100";

when others =>

y <= "1000";

end case;

end process;

end case_arch;