BCD Incrementor Lab VHDL Code (binary-coded-decimal and show digits on 7-segment LED's)

Project specification:
The binary-coded-decimal (BCD) format uses 4 bits to represent 10 decimal digits. For example, 259 is represented as "0010 0101 1001" in BCD format. A BCD incrementor adds 1 to a number in BCD format. For example, after incrementing, "0010 0101 1001" (i.e., 259) becomes "0010 0110 0000" (i.e., 260). We want to design the circuit and display the results on three 7- segment LED displays.

The input and output of the incrementor are
input:
b2, b1, b0: three 4-bit inputs representing 3 BCD digits and b2 is the most
significant digit.
output:
y2, y1, y0: three 4-bit outputs representing 3 incremented BCD digits and y2 is
the most significant digit.

BASIC INCREMENTOR VHDL CODE:

library ieee;
use ieee.std_logic_1164.all;
entity incrementor is
port
(
x: in std_logic_vector(3 downto 0);
y: out std_logic_vector(3 downto 0);
E: out std_logic
);
end incrementor;
architecture inc_arch of incrementor is
signal p: std_logic_vector(11 downto 0);
begin
--evaluate intermediate signals
p(11) <= (not x(3)) and x(2) and x(1) and x(0);
p(10) <= x(3) and (not x(2)) and (not x(1)) and (not x(0));
p(9) <= (not x(3)) and x(2) and (not x(0));
p(8) <= (not x(3)) and x(2) and (not x(1));
p(7) <= (not x(3)) and (not x(2)) and x(1) and x(0);
p(6) <= (not x(3)) and (not x(1)) and x(0);
p(5) <= (not x(3)) and (not x(0)) and x(1);
p(4) <= (not x(2)) and (not x(1)) and (not x(0));
p(3) <= (not x(3)) and (not x(0));
p(2) <= x(3) and x(2);
p(1) <= x(3) and x(0);
p(0) <= x(3) and x(1);
--get the final outputs using intermediate signal values
y(3) <= p(11) or p(10);
y(2) <= p(9) or p(8) or p(7);
y(1) <= p(6) or p(5);
y(0) <= p(4) or p(3);
E <= p(2) or p(1) or p(0);
end inc_arch; 

MUX VHDL CODE USED TO SELECT OUTPUT FROM INCREMENTOR:

--***************************************************************
--
-- Author: Sikander
--
-- File: mux_for_invertion.vhd
-- Design units:
-- ENTITY mux_for_invertion
-- ARCHITECTURE invertion
-- Purpose: to select particular input
-- Inputs: 2 4-bit inputs and ctl
-- Outputs: 1 4-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity mux is
port(
a,b: in std_logic_vector(3 downto 0);
ctl: in std_logic;
output: out std_logic_vector(3 downto 0)
);
end mux;
architecture selection of mux is
signal p,q: std_logic_vector(3 downto 0);
begin
p <= (not ctl) & (not ctl) & (not ctl) & (not ctl);
q <= ctl & ctl & ctl & ctl;
output <= (a and p) or (b and q);
end selection;

DISPLAY DIGITS ON 7-SEGMENT LED OF FPGA DEVICE VHDL CODE:

--***************************************************************
--
-- Author: Sikander
--
-- File: hex_toshow_LES.vhd
-- Design units:
-- ENTITY hex_toshow_LES
-- ARCHITECTURE arch
-- Purpose: to use LED
-- Inputs: 4-bit input
-- Outputs: 7-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity hex_toshow_LES is
port(
bin: in std_logic_vector(3 downto 0);
sseg: out std_logic_vector(6 downto 0)
);
end hex_toshow_LES;
architecture arch of hex_toshow_LES is
begin
with bin select
sseg <=
"1000000" when "0000",
"1111001" when "0001",
"0100100" when "0010",
"0110000" when "0011",
"0011001" when "0100",
"0010010" when "0101",
"0000010" when "0110",
"1111000" when "0111",
"0000000" when "1000",
"0010000" when "1001",
"0001000" when "1010",
"0000011" when "1011",
"1000110" when "1100",
"0100001" when "1101",
"0000110" when "1110",
"0001110" when others;

end arch;

FINAL BCD INCREMENTOR VHDL CODE:

--***************************************************************
--
-- Author: Sikander
--
-- File: bcd_inc.vhd
-- Design units:
-- ENTITY bcd_inc
-- ARCHITECTURE bcd_arch
-- Purpose: to function as 3 digit BCD incrementor
-- Inputs: 3 4-bit input
-- Outputs: 3 4-bit output
--
-- Library/Package:
-- ieee.std_logic_1164: to use std_logic
--
-- Software/Version:
-- Simulated by: Altera Quartus v11.0
-- Synthesized by: Altera Quartus v11.0
--
-- Revision History
-- Version 1.0:
-- Date: 9/29/2006
-- Comments: Original
--
--***************************************************************
library ieee;
use ieee.std_logic_1164.all;
entity bcd_inc is
port
(
b2, b1, b0: in std_logic_vector(3 downto 0);
y2, y1, y0: out std_logic_vector(3 downto 0)
);
end bcd_inc;
architecture bcd_arch of bcd_inc is
signal p,q,r,s: std_logic_vector(3 downto 0);
signal F,G: std_logic;
begin
b0_unit: entity work.incrementor(inc_arch)
port map(x=>b0, y=>y0, E=>F);
b1_unit: entity work.incrementor(inc_arch)
port map(x=>b1, y=>p, E=>G);
b2_unit: entity work.incrementor(inc_arch)
port map(x=>b2, y=>q);
mux1_unit: entity work.mux(selection)
port map(a=>b1, b=>p, ctl=>F, output=>y1);
mux2_unit: entity work.mux(selection)
port map(a=>b2, b=>q, ctl=>G, output=>y2);
end bcd_arch;